1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = common local_unnamed_addr global i32 0, align 4 10 11; Function Attrs: norecurse nounwind readnone 12define i64 @test_lleqsi(i32 signext %a, i32 signext %b) { 13; CHECK-LABEL: test_lleqsi: 14; CHECK: # %bb.0: # %entry 15; CHECK-NEXT: xor r3, r3, r4 16; CHECK-NEXT: cntlzw r3, r3 17; CHECK-NEXT: srwi r3, r3, 5 18; CHECK-NEXT: blr 19entry: 20 %cmp = icmp eq i32 %a, %b 21 %conv1 = zext i1 %cmp to i64 22 ret i64 %conv1 23} 24 25; Function Attrs: norecurse nounwind readnone 26define i64 @test_lleqsi_sext(i32 signext %a, i32 signext %b) { 27; CHECK-LABEL: test_lleqsi_sext: 28; CHECK: # %bb.0: # %entry 29; CHECK-NEXT: xor r3, r3, r4 30; CHECK-NEXT: cntlzw r3, r3 31; CHECK-NEXT: srwi r3, r3, 5 32; CHECK-NEXT: neg r3, r3 33; CHECK-NEXT: blr 34entry: 35 %cmp = icmp eq i32 %a, %b 36 %conv1 = sext i1 %cmp to i64 37 ret i64 %conv1 38} 39 40; Function Attrs: norecurse nounwind readnone 41define i64 @test_lleqsi_z(i32 signext %a) { 42; CHECK-LABEL: test_lleqsi_z: 43; CHECK: # %bb.0: # %entry 44; CHECK-NEXT: cntlzw r3, r3 45; CHECK-NEXT: srwi r3, r3, 5 46; CHECK-NEXT: blr 47entry: 48 %cmp = icmp eq i32 %a, 0 49 %conv1 = zext i1 %cmp to i64 50 ret i64 %conv1 51} 52 53; Function Attrs: norecurse nounwind readnone 54define i64 @test_lleqsi_sext_z(i32 signext %a) { 55; CHECK-LABEL: test_lleqsi_sext_z: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: cntlzw r3, r3 58; CHECK-NEXT: srwi r3, r3, 5 59; CHECK-NEXT: neg r3, r3 60; CHECK-NEXT: blr 61entry: 62 %cmp = icmp eq i32 %a, 0 63 %conv1 = sext i1 %cmp to i64 64 ret i64 %conv1 65} 66 67; Function Attrs: norecurse nounwind 68define void @test_lleqsi_store(i32 signext %a, i32 signext %b) { 69; CHECK-LABEL: test_lleqsi_store: 70; CHECK: # %bb.0: # %entry 71; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 72; CHECK-NEXT: xor r3, r3, r4 73; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 74; CHECK-NEXT: cntlzw r3, r3 75; CHECK-NEXT: srwi r3, r3, 5 76; CHECK-NEXT: stw r3, 0(r4) 77; CHECK-NEXT: blr 78entry: 79 %cmp = icmp eq i32 %a, %b 80 %conv = zext i1 %cmp to i32 81 store i32 %conv, i32* @glob, align 4 82 ret void 83} 84 85; Function Attrs: norecurse nounwind 86define void @test_lleqsi_sext_store(i32 signext %a, i32 signext %b) { 87; CHECK-LABEL: test_lleqsi_sext_store: 88; CHECK: # %bb.0: # %entry 89; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 90; CHECK-NEXT: xor r3, r3, r4 91; CHECK-NEXT: cntlzw r3, r3 92; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 93; CHECK-NEXT: srwi r3, r3, 5 94; CHECK-NEXT: neg r3, r3 95; CHECK-NEXT: stw r3, 0(r4) 96; CHECK-NEXT: blr 97entry: 98 %cmp = icmp eq i32 %a, %b 99 %sub = sext i1 %cmp to i32 100 store i32 %sub, i32* @glob, align 4 101 ret void 102} 103 104; Function Attrs: norecurse nounwind 105define void @test_lleqsi_z_store(i32 signext %a) { 106; CHECK-LABEL: test_lleqsi_z_store: 107; CHECK: # %bb.0: # %entry 108; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 109; CHECK-NEXT: cntlzw r3, r3 110; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 111; CHECK-NEXT: srwi r3, r3, 5 112; CHECK-NEXT: stw r3, 0(r4) 113; CHECK-NEXT: blr 114; CHECKNEXT: blr 115entry: 116 %cmp = icmp eq i32 %a, 0 117 %conv = zext i1 %cmp to i32 118 store i32 %conv, i32* @glob, align 4 119 ret void 120} 121 122; Function Attrs: norecurse nounwind 123define void @test_lleqsi_sext_z_store(i32 signext %a) { 124; CHECK-LABEL: test_lleqsi_sext_z_store: 125; CHECK: # %bb.0: # %entry 126; CHECK-NEXT: addis r4, r2, .LC0@toc@ha 127; CHECK-NEXT: cntlzw r3, r3 128; CHECK-NEXT: ld r4, .LC0@toc@l(r4) 129; CHECK-NEXT: srwi r3, r3, 5 130; CHECK-NEXT: neg r3, r3 131; CHECK-NEXT: stw r3, 0(r4) 132; CHECK-NEXT: blr 133entry: 134 %cmp = icmp eq i32 %a, 0 135 %sub = sext i1 %cmp to i32 136 store i32 %sub, i32* @glob, align 4 137 ret void 138} 139