1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ 3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ 6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ 7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl 8 9@glob = common local_unnamed_addr global i32 0, align 4 10 11define i64 @test_lllesi(i32 signext %a, i32 signext %b) { 12; CHECK-LABEL: test_lllesi: 13; CHECK: # %bb.0: # %entry 14; CHECK-NEXT: sub r3, r4, r3 15; CHECK-NEXT: rldicl r3, r3, 1, 63 16; CHECK-NEXT: xori r3, r3, 1 17; CHECK-NEXT: blr 18entry: 19 %cmp = icmp sle i32 %a, %b 20 %conv1 = zext i1 %cmp to i64 21 ret i64 %conv1 22} 23 24define i64 @test_lllesi_sext(i32 signext %a, i32 signext %b) { 25; CHECK-LABEL: test_lllesi_sext: 26; CHECK: # %bb.0: # %entry 27; CHECK-NEXT: sub r3, r4, r3 28; CHECK-NEXT: rldicl r3, r3, 1, 63 29; CHECK-NEXT: addi r3, r3, -1 30; CHECK-NEXT: blr 31entry: 32 %cmp = icmp sle i32 %a, %b 33 %conv1 = sext i1 %cmp to i64 34 ret i64 %conv1 35} 36 37define void @test_lllesi_store(i32 signext %a, i32 signext %b) { 38; CHECK-LABEL: test_lllesi_store: 39; CHECK: # %bb.0: # %entry 40; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 41; CHECK-NEXT: sub r3, r4, r3 42; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 43; CHECK-NEXT: rldicl r3, r3, 1, 63 44; CHECK-NEXT: xori r3, r3, 1 45; CHECK-NEXT: stw r3, 0(r4) 46; CHECK-NEXT: blr 47entry: 48 %cmp = icmp sle i32 %a, %b 49 %conv = zext i1 %cmp to i32 50 store i32 %conv, i32* @glob, align 4 51 ret void 52} 53 54define void @test_lllesi_sext_store(i32 signext %a, i32 signext %b) { 55; CHECK-LABEL: test_lllesi_sext_store: 56; CHECK: # %bb.0: # %entry 57; CHECK-NEXT: addis r5, r2, .LC0@toc@ha 58; CHECK-NEXT: sub r3, r4, r3 59; CHECK-NEXT: ld r4, .LC0@toc@l(r5) 60; CHECK-NEXT: rldicl r3, r3, 1, 63 61; CHECK-NEXT: addi r3, r3, -1 62; CHECK-NEXT: stw r3, 0(r4) 63; CHECK-NEXT: blr 64entry: 65 %cmp = icmp sle i32 %a, %b 66 %sub = sext i1 %cmp to i32 67 store i32 %sub, i32* @glob, align 4 68 ret void 69} 70