1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | \ 2; RUN: FileCheck %s -check-prefix=CHECK-LE 3; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | \ 4; RUN: FileCheck %s -check-prefix=CHECK-BE 5 6; Possible LE ShuffleVector masks (Case 1): 7; ShuffleVector((vector double)a, (vector double)b, 3, 1) 8; ShuffleVector((vector double)a, (vector double)b, 2, 1) 9; ShuffleVector((vector double)a, (vector double)b, 3, 0) 10; ShuffleVector((vector double)a, (vector double)b, 2, 0) 11; which targets at: 12; xxpermdi a, b, 0 13; xxpermdi a, b, 1 14; xxpermdi a, b, 2 15; xxpermdi a, b, 3 16; Possible LE Swap ShuffleVector masks (Case 2): 17; ShuffleVector((vector double)a, (vector double)b, 1, 3) 18; ShuffleVector((vector double)a, (vector double)b, 0, 3) 19; ShuffleVector((vector double)a, (vector double)b, 1, 2) 20; ShuffleVector((vector double)a, (vector double)b, 0, 2) 21; which targets at: 22; xxpermdi b, a, 0 23; xxpermdi b, a, 1 24; xxpermdi b, a, 2 25; xxpermdi b, a, 3 26; Possible LE ShuffleVector masks when a == b, b is undef (Case 3): 27; ShuffleVector((vector double)a, (vector double)a, 1, 1) 28; ShuffleVector((vector double)a, (vector double)a, 0, 1) 29; ShuffleVector((vector double)a, (vector double)a, 1, 0) 30; ShuffleVector((vector double)a, (vector double)a, 0, 0) 31; which targets at: 32; xxpermdi a, a, 0 33; xxpermdi a, a, 1 34; xxpermdi a, a, 2 35; xxpermdi a, a, 3 36 37; Possible BE ShuffleVector masks (Case 4): 38; ShuffleVector((vector double)a, (vector double)b, 0, 2) 39; ShuffleVector((vector double)a, (vector double)b, 0, 3) 40; ShuffleVector((vector double)a, (vector double)b, 1, 2) 41; ShuffleVector((vector double)a, (vector double)b, 1, 3) 42; which targets at: 43; xxpermdi a, b, 0 44; xxpermdi a, b, 1 45; xxpermdi a, b, 2 46; xxpermdi a, b, 3 47; Possible BE Swap ShuffleVector masks (Case 5): 48; ShuffleVector((vector double)a, (vector double)b, 2, 0) 49; ShuffleVector((vector double)a, (vector double)b, 3, 0) 50; ShuffleVector((vector double)a, (vector double)b, 2, 1) 51; ShuffleVector((vector double)a, (vector double)b, 3, 1) 52; which targets at: 53; xxpermdi b, a, 0 54; xxpermdi b, a, 1 55; xxpermdi b, a, 2 56; xxpermdi b, a, 3 57; Possible BE ShuffleVector masks when a == b, b is undef (Case 6): 58; ShuffleVector((vector double)a, (vector double)a, 0, 0) 59; ShuffleVector((vector double)a, (vector double)a, 0, 1) 60; ShuffleVector((vector double)a, (vector double)a, 1, 0) 61; ShuffleVector((vector double)a, (vector double)a, 1, 1) 62; which targets at: 63; xxpermdi a, a, 0 64; xxpermdi a, a, 1 65; xxpermdi a, a, 2 66; xxpermdi a, a, 3 67 68define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) { 69 entry: 70 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1> 71 ret <2 x double> %0 72; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_0 73; CHECK-LE: xxmrghd 34, 34, 35 74; CHECK-LE: blr 75} 76 77define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) { 78 entry: 79 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1> 80 ret <2 x double> %0 81; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_1 82; CHECK-LE: xxpermdi 34, 34, 35, 1 83; CHECK-LE: blr 84} 85 86define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) { 87 entry: 88 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0> 89 ret <2 x double> %0 90; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_2 91; CHECK-LE: xxpermdi 34, 34, 35, 2 92; CHECK-LE: blr 93} 94 95define <2 x double> @test_le_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) { 96 entry: 97 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0> 98 ret <2 x double> %0 99; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_v2f64_3 100; CHECK-LE: xxmrgld 34, 34, 35 101; CHECK-LE: blr 102} 103 104define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) { 105 entry: 106 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3> 107 ret <2 x double> %0 108; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_0 109; CHECK-LE: xxmrghd 34, 35, 34 110; CHECK-LE: blr 111} 112 113define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) { 114 entry: 115 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3> 116 ret <2 x double> %0 117; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_1 118; CHECK-LE: xxpermdi 34, 35, 34, 1 119; CHECK-LE: blr 120} 121 122define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) { 123 entry: 124 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2> 125 ret <2 x double> %0 126; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_2 127; CHECK-LE: xxpermdi 34, 35, 34, 2 128; CHECK-LE: blr 129} 130 131define <2 x double> @test_le_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) { 132 entry: 133 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2> 134 ret <2 x double> %0 135; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v2f64_v2f64_3 136; CHECK-LE: xxmrgld 34, 35, 34 137; CHECK-LE: blr 138} 139 140define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) { 141 entry: 142 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1> 143 ret <2 x double> %0 144; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_0 145; CHECK-LE: xxspltd 34, 34, 0 146; CHECK-LE: blr 147} 148 149define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) { 150 entry: 151 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1> 152 ret <2 x double> %0 153; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_1 154; CHECK-LE: blr 155} 156 157define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) { 158 entry: 159 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0> 160 ret <2 x double> %0 161; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_2 162; CHCECK-LE: xxswapd 34, 34 163} 164 165define <2 x double> @test_le_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) { 166 entry: 167 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0> 168 ret <2 x double> %0 169; CHECK-LE-LABEL: @test_le_vec_xxpermdi_v2f64_undef_3 170; CHECK-LE: xxspltd 34, 34, 1 171; CHECK-LE: blr 172} 173 174; Start testing BE 175define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) { 176 entry: 177 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 2> 178 ret <2 x double> %0 179; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_0 180; CHECK-BE: xxmrghd 34, 34, 35 181; CHECK-BE: blr 182} 183 184define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) { 185 entry: 186 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 0, i32 3> 187 ret <2 x double> %0 188; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_1 189; CHECK-BE: xxpermdi 34, 34, 35, 1 190; CHECK-BE: blr 191} 192 193define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) { 194 entry: 195 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 2> 196 ret <2 x double> %0 197; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_2 198; CHECK-BE: xxpermdi 34, 34, 35, 2 199; CHECK-BE: blr 200} 201 202define <2 x double> @test_be_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) { 203 entry: 204 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 1, i32 3> 205 ret <2 x double> %0 206; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_v2f64_3 207; CHECK-BE: xxmrgld 34, 34, 35 208; CHECK-BE: blr 209} 210 211define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_0(<2 x double> %VA, <2 x double> %VB) { 212 entry: 213 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 0> 214 ret <2 x double> %0 215; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_0 216; CHECK-BE: xxmrghd 34, 35, 34 217; CHECK-BE: blr 218} 219 220define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_1(<2 x double> %VA, <2 x double> %VB) { 221 entry: 222 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 2, i32 1> 223 ret <2 x double> %0 224; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_1 225; CHECK-BE: xxpermdi 34, 35, 34, 1 226; CHECK-BE: blr 227} 228 229define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_2(<2 x double> %VA, <2 x double> %VB) { 230 entry: 231 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 0> 232 ret <2 x double> %0 233; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_2 234; CHECK-BE: xxpermdi 34, 35, 34, 2 235; CHECK-BE: blr 236} 237 238define <2 x double> @test_be_swap_vec_xxpermdi_v2f64_v2f64_3(<2 x double> %VA, <2 x double> %VB) { 239 entry: 240 %0 = shufflevector <2 x double> %VA, <2 x double> %VB,<2 x i32> <i32 3, i32 1> 241 ret <2 x double> %0 242; CHECK-BE-LABEL: @test_be_swap_vec_xxpermdi_v2f64_v2f64_3 243; CHECK-BE: xxmrgld 34, 35, 34 244; CHECK-BE: blr 245} 246 247define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_0(<2 x double> %VA) { 248 entry: 249 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 0> 250 ret <2 x double> %0 251; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_0 252; CHECK-BE: xxspltd 34, 34, 0 253; CHECK-BE: blr 254} 255 256define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_1(<2 x double> %VA) { 257 entry: 258 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 0, i32 1> 259 ret <2 x double> %0 260; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_1 261; CHECK-BE: blr 262} 263 264define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_2(<2 x double> %VA) { 265 entry: 266 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 0> 267 ret <2 x double> %0 268; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_2 269; CHCECK-LE: xxswapd 34, 34 270} 271 272define <2 x double> @test_be_vec_xxpermdi_v2f64_undef_3(<2 x double> %VA) { 273 entry: 274 %0 = shufflevector <2 x double> %VA, <2 x double> undef, <2 x i32> <i32 1, i32 1> 275 ret <2 x double> %0 276; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v2f64_undef_3 277; CHECK-BE: xxspltd 34, 34, 1 278; CHECK-BE: blr 279} 280 281; More test cases to test different types of vector inputs 282define <16 x i8> @test_be_vec_xxpermdi_v16i8_v16i8(<16 x i8> %VA, <16 x i8> %VB) { 283 entry: 284 %0 = shufflevector <16 x i8> %VA, <16 x i8> %VB,<16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19> 285 ret <16 x i8> %0 286; CHECK-BE-LABEL: @test_be_vec_xxpermdi_v16i8_v16i8 287; CHECK-BE: xxpermdi 34, 34, 35, 1 288; CHECK-BE: blr 289} 290 291define <8 x i16> @test_le_swap_vec_xxpermdi_v8i16_v8i16(<8 x i16> %VA, <8 x i16> %VB) { 292 entry: 293 %0 = shufflevector <8 x i16> %VA, <8 x i16> %VB,<8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15> 294 ret <8 x i16> %0 295; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v8i16_v8i16 296; CHECK-LE: xxpermdi 34, 35, 34, 1 297; CHECK-LE: blr 298} 299 300define <4 x i32> @test_le_swap_vec_xxpermdi_v4i32_v4i32(<4 x i32> %VA, <4 x i32> %VB) { 301 entry: 302 %0 = shufflevector <4 x i32> %VA, <4 x i32> %VB,<4 x i32> <i32 0, i32 1, i32 6, i32 7> 303 ret <4 x i32> %0 304; CHECK-LE-LABEL: @test_le_swap_vec_xxpermdi_v4i32_v4i32 305; CHECK-LE: xxpermdi 34, 35, 34, 1 306; CHECK-LE: blr 307} 308