1; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s 2; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-PWR9 %s 3 4define <4 x i32> @testSpill(<4 x i32> %a, <4 x i32> %b) { 5 6; CHECK-LABEL: testSpill: 7; CHECK-DAG: li [[REG48:[0-9]+]], 48 8; CHECK-DAG: li [[REG64:[0-9]+]], 64 9; CHECK-DAG: li [[REG80:[0-9]+]], 80 10; CHECK-DAG: li [[REG96:[0-9]+]], 96 11; CHECK-DAG: stxvd2x 60, 1, [[REG48]] # 16-byte Folded Spill 12; CHECK-DAG: stxvd2x 61, 1, [[REG64]] # 16-byte Folded Spill 13; CHECK-DAG: stxvd2x 62, 1, [[REG80]] # 16-byte Folded Spill 14; CHECK-DAG: stxvd2x 63, 1, [[REG96]] # 16-byte Folded Spill 15; CHECK: .LBB0_3 16; CHECK-DAG: li [[REG96_LD:[0-9]+]], 96 17; CHECK-DAG: li [[REG80_LD:[0-9]+]], 80 18; CHECK-DAG: li [[REG64_LD:[0-9]+]], 64 19; CHECK-DAG: li [[REG48_LD:[0-9]+]], 48 20; CHECK-DAG: lxvd2x 63, 1, [[REG96_LD]] # 16-byte Folded Reload 21; CHECK-DAG: lxvd2x 62, 1, [[REG80_LD]] # 16-byte Folded Reload 22; CHECK-DAG: lxvd2x 61, 1, [[REG64_LD]] # 16-byte Folded Reload 23; CHECK-DAG: lxvd2x 60, 1, [[REG48_LD]] # 16-byte Folded Reload 24; CHECK: mtlr 0 25; CHECK-NEXT: blr 26; 27; CHECK-PWR9-LABEL: testSpill: 28; CHECK-PWR9-DAG: stxv 62, 64(1) # 16-byte Folded Spill 29; CHECK-PWR9-DAG: stxv 63, 80(1) # 16-byte Folded Spill 30; CHECK-PWR9-DAG: stxv 60, 32(1) # 16-byte Folded Spill 31; CHECK-PWR9-DAG: stxv 61, 48(1) # 16-byte Folded Spill 32; CHECK-PWR9-NOT: NOT 33; CHECK-PWR9-DAG: lxv 63, 80(1) # 16-byte Folded Reload 34; CHECK-PWR9-DAG: lxv 62, 64(1) # 16-byte Folded Reload 35; CHECK-PWR9-DAG: lxv 61, 48(1) # 16-byte Folded Reload 36; CHECK-PWR9-DAG: lxv 60, 32(1) # 16-byte Folded Reload 37; CHECK-PWR9: mtlr 0 38; CHECK-PWR9-NEXT: blr 39 40entry: 41 %0 = tail call i32 @llvm.ppc.altivec.vcmpgtsw.p(i32 2, <4 x i32> %a, <4 x i32> %b) 42 %tobool = icmp eq i32 %0, 0 43 br i1 %tobool, label %if.else, label %if.then 44 45if.then: ; preds = %entry 46 %call = tail call <4 x i32> @test1(<4 x i32> %a, <4 x i32> %b) 47 br label %if.end 48 49if.else: ; preds = %entry 50 %call1 = tail call <4 x i32> @test2(<4 x i32> %b, <4 x i32> %a) 51 br label %if.end 52 53if.end: ; preds = %if.else, %if.then 54 %c.0.in = phi <4 x i32> [ %call, %if.then ], [ %call1, %if.else ] 55 %call3 = tail call <4 x i32> @test1(<4 x i32> %b, <4 x i32> %a) 56 %call5 = tail call <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) 57 %add4 = add <4 x i32> %a, <i32 0, i32 0, i32 2, i32 2> 58 %add6 = add <4 x i32> %add4, %c.0.in 59 %c.0 = add <4 x i32> %add6, %call3 60 %add7 = add <4 x i32> %c.0, %call5 61 ret <4 x i32> %add7 62} 63 64; Function Attrs: nounwind readnone 65declare i32 @llvm.ppc.altivec.vcmpgtsw.p(i32, <4 x i32>, <4 x i32>) 66declare <4 x i32> @test1(<4 x i32>, <4 x i32>) 67declare <4 x i32> @test2(<4 x i32>, <4 x i32>) 68