1; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \ 2; RUN: -disable-block-placement < %s \ 3; RUN: | llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \ 4; RUN: | FileCheck -check-prefix=RV32IC %s 5 6; This acts as a sanity check for the codegen instruction compression path, 7; verifying that the assembled file contains compressed instructions when 8; expected. Handling of the compressed ISA is implemented so the same 9; transformation patterns should be used whether compressing an input .s file or 10; compressing codegen output. This file contains sanity checks to ensure that is 11; working as expected. Particular care should be taken to test pseudo 12; instructions. 13 14; Note: TODOs in this file are only appropriate if they highlight a case where 15; a generated instruction that can be compressed by an existing pattern isn't. 16; It may be useful to have tests that indicate where better compression would be 17; possible if alternative codegen choices were made, but they belong in a 18; different test file. 19 20define i32 @simple_arith(i32 %a, i32 %b) nounwind { 21; RV32IC-LABEL: simple_arith: 22; RV32IC: c.srai a1, 9 23; RV32IC-NEXT: addi a2, a0, 1 24; RV32IC-NEXT: c.andi a2, 11 25; RV32IC-NEXT: c.slli a2, 7 26; RV32IC-NEXT: c.add a1, a2 27; RV32IC-NEXT: sub a0, a1, a0 28; RV32IC-NEXT: c.jr ra 29 %1 = add i32 %a, 1 30 %2 = and i32 %1, 11 31 %3 = shl i32 %2, 7 32 %4 = ashr i32 %b, 9 33 %5 = add i32 %3, %4 34 %6 = sub i32 %5, %a 35 ret i32 %6 36} 37 38define i32 @select(i32 %a, i32 *%b) nounwind { 39; RV32IC-LABEL: select: 40; RV32IC: c.lw a2, 0(a1) 41; RV32IC-NEXT: c.beqz a2, 4 42; RV32IC-NEXT: c.mv a0, a2 43; RV32IC-NEXT: c.lw a2, 0(a1) 44; RV32IC-NEXT: c.bnez a2, 4 45; RV32IC-NEXT: c.mv a0, a2 46; RV32IC-NEXT: c.lw a2, 0(a1) 47; RV32IC-NEXT: bltu a2, a0, 6 48; RV32IC-NEXT: c.mv a0, a2 49; RV32IC-NEXT: c.lw a2, 0(a1) 50; RV32IC-NEXT: bgeu a0, a2, 6 51; RV32IC-NEXT: c.mv a0, a2 52; RV32IC-NEXT: c.lw a2, 0(a1) 53; RV32IC-NEXT: bltu a0, a2, 6 54; RV32IC-NEXT: c.mv a0, a2 55; RV32IC-NEXT: c.lw a2, 0(a1) 56; RV32IC-NEXT: bgeu a2, a0, 6 57; RV32IC-NEXT: c.mv a0, a2 58; RV32IC-NEXT: c.lw a2, 0(a1) 59; RV32IC-NEXT: blt a2, a0, 6 60; RV32IC-NEXT: c.mv a0, a2 61; RV32IC-NEXT: c.lw a2, 0(a1) 62; RV32IC-NEXT: bge a0, a2, 6 63; RV32IC-NEXT: c.mv a0, a2 64; RV32IC-NEXT: c.lw a2, 0(a1) 65; RV32IC-NEXT: blt a0, a2, 6 66; RV32IC-NEXT: c.mv a0, a2 67; RV32IC-NEXT: c.lw a1, 0(a1) 68; RV32IC-NEXT: bge a1, a0, 6 69; RV32IC-NEXT: c.mv a0, a1 70; RV32IC-NEXT: c.jr ra 71 %val1 = load volatile i32, i32* %b 72 %tst1 = icmp eq i32 0, %val1 73 %val2 = select i1 %tst1, i32 %a, i32 %val1 74 75 %val3 = load volatile i32, i32* %b 76 %tst2 = icmp ne i32 0, %val3 77 %val4 = select i1 %tst2, i32 %val2, i32 %val3 78 79 %val5 = load volatile i32, i32* %b 80 %tst3 = icmp ugt i32 %val4, %val5 81 %val6 = select i1 %tst3, i32 %val4, i32 %val5 82 83 %val7 = load volatile i32, i32* %b 84 %tst4 = icmp uge i32 %val6, %val7 85 %val8 = select i1 %tst4, i32 %val6, i32 %val7 86 87 %val9 = load volatile i32, i32* %b 88 %tst5 = icmp ult i32 %val8, %val9 89 %val10 = select i1 %tst5, i32 %val8, i32 %val9 90 91 %val11 = load volatile i32, i32* %b 92 %tst6 = icmp ule i32 %val10, %val11 93 %val12 = select i1 %tst6, i32 %val10, i32 %val11 94 95 %val13 = load volatile i32, i32* %b 96 %tst7 = icmp sgt i32 %val12, %val13 97 %val14 = select i1 %tst7, i32 %val12, i32 %val13 98 99 %val15 = load volatile i32, i32* %b 100 %tst8 = icmp sge i32 %val14, %val15 101 %val16 = select i1 %tst8, i32 %val14, i32 %val15 102 103 %val17 = load volatile i32, i32* %b 104 %tst9 = icmp slt i32 %val16, %val17 105 %val18 = select i1 %tst9, i32 %val16, i32 %val17 106 107 %val19 = load volatile i32, i32* %b 108 %tst10 = icmp sle i32 %val18, %val19 109 %val20 = select i1 %tst10, i32 %val18, i32 %val19 110 111 ret i32 %val20 112} 113 114define i32 @pos_tiny() nounwind { 115; RV32IC-LABEL: pos_tiny: 116; RV32IC: c.li a0, 18 117; RV32IC-NEXT: c.jr ra 118 ret i32 18 119} 120 121define i32 @pos_i32() nounwind { 122; RV32IC-LABEL: pos_i32: 123; RV32IC: lui a0, 423811 124; RV32IC-NEXT: addi a0, a0, -1297 125; RV32IC-NEXT: c.jr ra 126 ret i32 1735928559 127} 128 129define i32 @pos_i32_half_compressible() nounwind { 130; RV32IC-LABEL: pos_i32_half_compressible: 131; RV32IC: lui a0, 423810 132; RV32IC-NEXT: c.addi a0, 28 133; RV32IC-NEXT: c.jr ra 134 ret i32 1735925788 135} 136 137 138define i32 @neg_tiny() nounwind { 139; RV32IC-LABEL: neg_tiny: 140; RV32IC: c.li a0, -19 141; RV32IC-NEXT: c.jr ra 142 ret i32 -19 143} 144 145define i32 @neg_i32() nounwind { 146; RV32IC-LABEL: neg_i32: 147; RV32IC: lui a0, 912092 148; RV32IC-NEXT: addi a0, a0, -273 149; RV32IC-NEXT: c.jr ra 150 ret i32 -559038737 151} 152 153define i32 @pos_i32_hi20_only() nounwind { 154; RV32IC-LABEL: pos_i32_hi20_only: 155; RV32IC: c.lui a0, 16 156; RV32IC-NEXT: c.jr ra 157 ret i32 65536 158} 159 160define i32 @neg_i32_hi20_only() nounwind { 161; RV32IC-LABEL: neg_i32_hi20_only: 162; RV32IC: c.lui a0, 1048560 163; RV32IC-NEXT: c.jr ra 164 ret i32 -65536 165} 166