1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32I %s 4; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ 5; RUN: | FileCheck -check-prefix=RV32IM %s 6 7define i32 @udiv(i32 %a, i32 %b) nounwind { 8; RV32I-LABEL: udiv: 9; RV32I: # %bb.0: 10; RV32I-NEXT: addi sp, sp, -16 11; RV32I-NEXT: sw ra, 12(sp) 12; RV32I-NEXT: call __udivsi3 13; RV32I-NEXT: lw ra, 12(sp) 14; RV32I-NEXT: addi sp, sp, 16 15; RV32I-NEXT: ret 16; 17; RV32IM-LABEL: udiv: 18; RV32IM: # %bb.0: 19; RV32IM-NEXT: divu a0, a0, a1 20; RV32IM-NEXT: ret 21 %1 = udiv i32 %a, %b 22 ret i32 %1 23} 24 25define i32 @udiv_constant(i32 %a) nounwind { 26; RV32I-LABEL: udiv_constant: 27; RV32I: # %bb.0: 28; RV32I-NEXT: addi sp, sp, -16 29; RV32I-NEXT: sw ra, 12(sp) 30; RV32I-NEXT: addi a1, zero, 5 31; RV32I-NEXT: call __udivsi3 32; RV32I-NEXT: lw ra, 12(sp) 33; RV32I-NEXT: addi sp, sp, 16 34; RV32I-NEXT: ret 35; 36; RV32IM-LABEL: udiv_constant: 37; RV32IM: # %bb.0: 38; RV32IM-NEXT: lui a1, 838861 39; RV32IM-NEXT: addi a1, a1, -819 40; RV32IM-NEXT: mulhu a0, a0, a1 41; RV32IM-NEXT: srli a0, a0, 2 42; RV32IM-NEXT: ret 43 %1 = udiv i32 %a, 5 44 ret i32 %1 45} 46 47define i32 @udiv_pow2(i32 %a) nounwind { 48; RV32I-LABEL: udiv_pow2: 49; RV32I: # %bb.0: 50; RV32I-NEXT: srli a0, a0, 3 51; RV32I-NEXT: ret 52; 53; RV32IM-LABEL: udiv_pow2: 54; RV32IM: # %bb.0: 55; RV32IM-NEXT: srli a0, a0, 3 56; RV32IM-NEXT: ret 57 %1 = udiv i32 %a, 8 58 ret i32 %1 59} 60 61define i64 @udiv64(i64 %a, i64 %b) nounwind { 62; RV32I-LABEL: udiv64: 63; RV32I: # %bb.0: 64; RV32I-NEXT: addi sp, sp, -16 65; RV32I-NEXT: sw ra, 12(sp) 66; RV32I-NEXT: call __udivdi3 67; RV32I-NEXT: lw ra, 12(sp) 68; RV32I-NEXT: addi sp, sp, 16 69; RV32I-NEXT: ret 70; 71; RV32IM-LABEL: udiv64: 72; RV32IM: # %bb.0: 73; RV32IM-NEXT: addi sp, sp, -16 74; RV32IM-NEXT: sw ra, 12(sp) 75; RV32IM-NEXT: call __udivdi3 76; RV32IM-NEXT: lw ra, 12(sp) 77; RV32IM-NEXT: addi sp, sp, 16 78; RV32IM-NEXT: ret 79 %1 = udiv i64 %a, %b 80 ret i64 %1 81} 82 83define i64 @udiv64_constant(i64 %a) nounwind { 84; RV32I-LABEL: udiv64_constant: 85; RV32I: # %bb.0: 86; RV32I-NEXT: addi sp, sp, -16 87; RV32I-NEXT: sw ra, 12(sp) 88; RV32I-NEXT: addi a2, zero, 5 89; RV32I-NEXT: mv a3, zero 90; RV32I-NEXT: call __udivdi3 91; RV32I-NEXT: lw ra, 12(sp) 92; RV32I-NEXT: addi sp, sp, 16 93; RV32I-NEXT: ret 94; 95; RV32IM-LABEL: udiv64_constant: 96; RV32IM: # %bb.0: 97; RV32IM-NEXT: addi sp, sp, -16 98; RV32IM-NEXT: sw ra, 12(sp) 99; RV32IM-NEXT: addi a2, zero, 5 100; RV32IM-NEXT: mv a3, zero 101; RV32IM-NEXT: call __udivdi3 102; RV32IM-NEXT: lw ra, 12(sp) 103; RV32IM-NEXT: addi sp, sp, 16 104; RV32IM-NEXT: ret 105 %1 = udiv i64 %a, 5 106 ret i64 %1 107} 108 109define i32 @sdiv(i32 %a, i32 %b) nounwind { 110; RV32I-LABEL: sdiv: 111; RV32I: # %bb.0: 112; RV32I-NEXT: addi sp, sp, -16 113; RV32I-NEXT: sw ra, 12(sp) 114; RV32I-NEXT: call __divsi3 115; RV32I-NEXT: lw ra, 12(sp) 116; RV32I-NEXT: addi sp, sp, 16 117; RV32I-NEXT: ret 118; 119; RV32IM-LABEL: sdiv: 120; RV32IM: # %bb.0: 121; RV32IM-NEXT: div a0, a0, a1 122; RV32IM-NEXT: ret 123 %1 = sdiv i32 %a, %b 124 ret i32 %1 125} 126 127define i32 @sdiv_constant(i32 %a) nounwind { 128; RV32I-LABEL: sdiv_constant: 129; RV32I: # %bb.0: 130; RV32I-NEXT: addi sp, sp, -16 131; RV32I-NEXT: sw ra, 12(sp) 132; RV32I-NEXT: addi a1, zero, 5 133; RV32I-NEXT: call __divsi3 134; RV32I-NEXT: lw ra, 12(sp) 135; RV32I-NEXT: addi sp, sp, 16 136; RV32I-NEXT: ret 137; 138; RV32IM-LABEL: sdiv_constant: 139; RV32IM: # %bb.0: 140; RV32IM-NEXT: lui a1, 419430 141; RV32IM-NEXT: addi a1, a1, 1639 142; RV32IM-NEXT: mulh a0, a0, a1 143; RV32IM-NEXT: srli a1, a0, 31 144; RV32IM-NEXT: srai a0, a0, 1 145; RV32IM-NEXT: add a0, a0, a1 146; RV32IM-NEXT: ret 147 %1 = sdiv i32 %a, 5 148 ret i32 %1 149} 150 151define i32 @sdiv_pow2(i32 %a) nounwind { 152; RV32I-LABEL: sdiv_pow2: 153; RV32I: # %bb.0: 154; RV32I-NEXT: srai a1, a0, 31 155; RV32I-NEXT: srli a1, a1, 29 156; RV32I-NEXT: add a0, a0, a1 157; RV32I-NEXT: srai a0, a0, 3 158; RV32I-NEXT: ret 159; 160; RV32IM-LABEL: sdiv_pow2: 161; RV32IM: # %bb.0: 162; RV32IM-NEXT: srai a1, a0, 31 163; RV32IM-NEXT: srli a1, a1, 29 164; RV32IM-NEXT: add a0, a0, a1 165; RV32IM-NEXT: srai a0, a0, 3 166; RV32IM-NEXT: ret 167 %1 = sdiv i32 %a, 8 168 ret i32 %1 169} 170 171define i64 @sdiv64(i64 %a, i64 %b) nounwind { 172; RV32I-LABEL: sdiv64: 173; RV32I: # %bb.0: 174; RV32I-NEXT: addi sp, sp, -16 175; RV32I-NEXT: sw ra, 12(sp) 176; RV32I-NEXT: call __divdi3 177; RV32I-NEXT: lw ra, 12(sp) 178; RV32I-NEXT: addi sp, sp, 16 179; RV32I-NEXT: ret 180; 181; RV32IM-LABEL: sdiv64: 182; RV32IM: # %bb.0: 183; RV32IM-NEXT: addi sp, sp, -16 184; RV32IM-NEXT: sw ra, 12(sp) 185; RV32IM-NEXT: call __divdi3 186; RV32IM-NEXT: lw ra, 12(sp) 187; RV32IM-NEXT: addi sp, sp, 16 188; RV32IM-NEXT: ret 189 %1 = sdiv i64 %a, %b 190 ret i64 %1 191} 192 193define i64 @sdiv64_constant(i64 %a) nounwind { 194; RV32I-LABEL: sdiv64_constant: 195; RV32I: # %bb.0: 196; RV32I-NEXT: addi sp, sp, -16 197; RV32I-NEXT: sw ra, 12(sp) 198; RV32I-NEXT: addi a2, zero, 5 199; RV32I-NEXT: mv a3, zero 200; RV32I-NEXT: call __divdi3 201; RV32I-NEXT: lw ra, 12(sp) 202; RV32I-NEXT: addi sp, sp, 16 203; RV32I-NEXT: ret 204; 205; RV32IM-LABEL: sdiv64_constant: 206; RV32IM: # %bb.0: 207; RV32IM-NEXT: addi sp, sp, -16 208; RV32IM-NEXT: sw ra, 12(sp) 209; RV32IM-NEXT: addi a2, zero, 5 210; RV32IM-NEXT: mv a3, zero 211; RV32IM-NEXT: call __divdi3 212; RV32IM-NEXT: lw ra, 12(sp) 213; RV32IM-NEXT: addi sp, sp, 16 214; RV32IM-NEXT: ret 215 %1 = sdiv i64 %a, 5 216 ret i64 %1 217} 218