1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \ 3; RUN: | FileCheck -check-prefix=RV32IF %s 4 5define i32 @fcmp_false(float %a, float %b) nounwind { 6; RV32IF-LABEL: fcmp_false: 7; RV32IF: # %bb.0: 8; RV32IF-NEXT: mv a0, zero 9; RV32IF-NEXT: ret 10 %1 = fcmp false float %a, %b 11 %2 = zext i1 %1 to i32 12 ret i32 %2 13} 14 15define i32 @fcmp_oeq(float %a, float %b) nounwind { 16; RV32IF-LABEL: fcmp_oeq: 17; RV32IF: # %bb.0: 18; RV32IF-NEXT: fmv.w.x ft0, a1 19; RV32IF-NEXT: fmv.w.x ft1, a0 20; RV32IF-NEXT: feq.s a0, ft1, ft0 21; RV32IF-NEXT: ret 22 %1 = fcmp oeq float %a, %b 23 %2 = zext i1 %1 to i32 24 ret i32 %2 25} 26 27define i32 @fcmp_ogt(float %a, float %b) nounwind { 28; RV32IF-LABEL: fcmp_ogt: 29; RV32IF: # %bb.0: 30; RV32IF-NEXT: fmv.w.x ft0, a0 31; RV32IF-NEXT: fmv.w.x ft1, a1 32; RV32IF-NEXT: flt.s a0, ft1, ft0 33; RV32IF-NEXT: ret 34 %1 = fcmp ogt float %a, %b 35 %2 = zext i1 %1 to i32 36 ret i32 %2 37} 38 39define i32 @fcmp_oge(float %a, float %b) nounwind { 40; RV32IF-LABEL: fcmp_oge: 41; RV32IF: # %bb.0: 42; RV32IF-NEXT: fmv.w.x ft0, a0 43; RV32IF-NEXT: fmv.w.x ft1, a1 44; RV32IF-NEXT: fle.s a0, ft1, ft0 45; RV32IF-NEXT: ret 46 %1 = fcmp oge float %a, %b 47 %2 = zext i1 %1 to i32 48 ret i32 %2 49} 50 51define i32 @fcmp_olt(float %a, float %b) nounwind { 52; RV32IF-LABEL: fcmp_olt: 53; RV32IF: # %bb.0: 54; RV32IF-NEXT: fmv.w.x ft0, a1 55; RV32IF-NEXT: fmv.w.x ft1, a0 56; RV32IF-NEXT: flt.s a0, ft1, ft0 57; RV32IF-NEXT: ret 58 %1 = fcmp olt float %a, %b 59 %2 = zext i1 %1 to i32 60 ret i32 %2 61} 62 63define i32 @fcmp_ole(float %a, float %b) nounwind { 64; RV32IF-LABEL: fcmp_ole: 65; RV32IF: # %bb.0: 66; RV32IF-NEXT: fmv.w.x ft0, a1 67; RV32IF-NEXT: fmv.w.x ft1, a0 68; RV32IF-NEXT: fle.s a0, ft1, ft0 69; RV32IF-NEXT: ret 70 %1 = fcmp ole float %a, %b 71 %2 = zext i1 %1 to i32 72 ret i32 %2 73} 74 75define i32 @fcmp_one(float %a, float %b) nounwind { 76; RV32IF-LABEL: fcmp_one: 77; RV32IF: # %bb.0: 78; RV32IF-NEXT: fmv.w.x ft0, a0 79; RV32IF-NEXT: fmv.w.x ft1, a1 80; RV32IF-NEXT: feq.s a0, ft1, ft1 81; RV32IF-NEXT: feq.s a1, ft0, ft0 82; RV32IF-NEXT: and a0, a1, a0 83; RV32IF-NEXT: feq.s a1, ft0, ft1 84; RV32IF-NEXT: not a1, a1 85; RV32IF-NEXT: seqz a0, a0 86; RV32IF-NEXT: xori a0, a0, 1 87; RV32IF-NEXT: and a0, a1, a0 88; RV32IF-NEXT: ret 89 %1 = fcmp one float %a, %b 90 %2 = zext i1 %1 to i32 91 ret i32 %2 92} 93 94define i32 @fcmp_ord(float %a, float %b) nounwind { 95; RV32IF-LABEL: fcmp_ord: 96; RV32IF: # %bb.0: 97; RV32IF-NEXT: fmv.w.x ft0, a1 98; RV32IF-NEXT: feq.s a1, ft0, ft0 99; RV32IF-NEXT: fmv.w.x ft0, a0 100; RV32IF-NEXT: feq.s a0, ft0, ft0 101; RV32IF-NEXT: and a0, a0, a1 102; RV32IF-NEXT: seqz a0, a0 103; RV32IF-NEXT: xori a0, a0, 1 104; RV32IF-NEXT: ret 105 %1 = fcmp ord float %a, %b 106 %2 = zext i1 %1 to i32 107 ret i32 %2 108} 109 110define i32 @fcmp_ueq(float %a, float %b) nounwind { 111; RV32IF-LABEL: fcmp_ueq: 112; RV32IF: # %bb.0: 113; RV32IF-NEXT: fmv.w.x ft0, a1 114; RV32IF-NEXT: fmv.w.x ft1, a0 115; RV32IF-NEXT: feq.s a0, ft1, ft0 116; RV32IF-NEXT: feq.s a1, ft0, ft0 117; RV32IF-NEXT: feq.s a2, ft1, ft1 118; RV32IF-NEXT: and a1, a2, a1 119; RV32IF-NEXT: seqz a1, a1 120; RV32IF-NEXT: or a0, a0, a1 121; RV32IF-NEXT: ret 122 %1 = fcmp ueq float %a, %b 123 %2 = zext i1 %1 to i32 124 ret i32 %2 125} 126 127define i32 @fcmp_ugt(float %a, float %b) nounwind { 128; RV32IF-LABEL: fcmp_ugt: 129; RV32IF: # %bb.0: 130; RV32IF-NEXT: fmv.w.x ft0, a1 131; RV32IF-NEXT: fmv.w.x ft1, a0 132; RV32IF-NEXT: fle.s a0, ft1, ft0 133; RV32IF-NEXT: xori a0, a0, 1 134; RV32IF-NEXT: ret 135 %1 = fcmp ugt float %a, %b 136 %2 = zext i1 %1 to i32 137 ret i32 %2 138} 139 140define i32 @fcmp_uge(float %a, float %b) nounwind { 141; RV32IF-LABEL: fcmp_uge: 142; RV32IF: # %bb.0: 143; RV32IF-NEXT: fmv.w.x ft0, a1 144; RV32IF-NEXT: fmv.w.x ft1, a0 145; RV32IF-NEXT: flt.s a0, ft1, ft0 146; RV32IF-NEXT: xori a0, a0, 1 147; RV32IF-NEXT: ret 148 %1 = fcmp uge float %a, %b 149 %2 = zext i1 %1 to i32 150 ret i32 %2 151} 152 153define i32 @fcmp_ult(float %a, float %b) nounwind { 154; RV32IF-LABEL: fcmp_ult: 155; RV32IF: # %bb.0: 156; RV32IF-NEXT: fmv.w.x ft0, a0 157; RV32IF-NEXT: fmv.w.x ft1, a1 158; RV32IF-NEXT: fle.s a0, ft1, ft0 159; RV32IF-NEXT: xori a0, a0, 1 160; RV32IF-NEXT: ret 161 %1 = fcmp ult float %a, %b 162 %2 = zext i1 %1 to i32 163 ret i32 %2 164} 165 166define i32 @fcmp_ule(float %a, float %b) nounwind { 167; RV32IF-LABEL: fcmp_ule: 168; RV32IF: # %bb.0: 169; RV32IF-NEXT: fmv.w.x ft0, a0 170; RV32IF-NEXT: fmv.w.x ft1, a1 171; RV32IF-NEXT: flt.s a0, ft1, ft0 172; RV32IF-NEXT: xori a0, a0, 1 173; RV32IF-NEXT: ret 174 %1 = fcmp ule float %a, %b 175 %2 = zext i1 %1 to i32 176 ret i32 %2 177} 178 179define i32 @fcmp_une(float %a, float %b) nounwind { 180; RV32IF-LABEL: fcmp_une: 181; RV32IF: # %bb.0: 182; RV32IF-NEXT: fmv.w.x ft0, a1 183; RV32IF-NEXT: fmv.w.x ft1, a0 184; RV32IF-NEXT: feq.s a0, ft1, ft0 185; RV32IF-NEXT: xori a0, a0, 1 186; RV32IF-NEXT: ret 187 %1 = fcmp une float %a, %b 188 %2 = zext i1 %1 to i32 189 ret i32 %2 190} 191 192define i32 @fcmp_uno(float %a, float %b) nounwind { 193; RV32IF-LABEL: fcmp_uno: 194; RV32IF: # %bb.0: 195; RV32IF-NEXT: fmv.w.x ft0, a1 196; RV32IF-NEXT: feq.s a1, ft0, ft0 197; RV32IF-NEXT: fmv.w.x ft0, a0 198; RV32IF-NEXT: feq.s a0, ft0, ft0 199; RV32IF-NEXT: and a0, a0, a1 200; RV32IF-NEXT: seqz a0, a0 201; RV32IF-NEXT: ret 202 %1 = fcmp uno float %a, %b 203 %2 = zext i1 %1 to i32 204 ret i32 %2 205} 206 207define i32 @fcmp_true(float %a, float %b) nounwind { 208; RV32IF-LABEL: fcmp_true: 209; RV32IF: # %bb.0: 210; RV32IF-NEXT: addi a0, zero, 1 211; RV32IF-NEXT: ret 212 %1 = fcmp true float %a, %b 213 %2 = zext i1 %1 to i32 214 ret i32 %2 215} 216