• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
2
3; Stackmap Header: no constants - 6 callsites
4; CHECK:        .section .llvm_stackmaps
5; CHECK-NEXT:   __LLVM_StackMaps:
6; Header
7; CHECK-NEXT:   .byte 3
8; CHECK-NEXT:   .byte 0
9; CHECK-NEXT:   .short 0
10; Num Functions
11; CHECK-NEXT:   .long 8
12; Num Constants
13; CHECK-NEXT:   .long 0
14; Num Callsites
15; CHECK-NEXT:   .long 8
16
17; Functions and stack size
18; CHECK-NEXT:   .quad test
19; CHECK-NEXT:   .quad 160
20; CHECK-NEXT:   .quad 1
21; CHECK-NEXT:   .quad property_access1
22; CHECK-NEXT:   .quad 160
23; CHECK-NEXT:   .quad 1
24; CHECK-NEXT:   .quad property_access2
25; CHECK-NEXT:   .quad 168
26; CHECK-NEXT:   .quad 1
27; CHECK-NEXT:   .quad property_access3
28; CHECK-NEXT:   .quad 168
29; CHECK-NEXT:   .quad 1
30; CHECK-NEXT:   .quad anyreg_test1
31; CHECK-NEXT:   .quad 160
32; CHECK-NEXT:   .quad 1
33; CHECK-NEXT:   .quad anyreg_test2
34; CHECK-NEXT:   .quad 160
35; CHECK-NEXT:   .quad 1
36; CHECK-NEXT:   .quad patchpoint_spilldef
37; CHECK-NEXT:   .quad 168
38; CHECK-NEXT:   .quad 1
39; CHECK-NEXT:   .quad patchpoint_spillargs
40; CHECK-NEXT:   .quad 192
41; CHECK-NEXT:   .quad 1
42
43; No constants
44
45; Callsites
46; test
47; CHECK:        .long   .L{{.*}}-test
48; CHECK-NEXT:   .short  0
49; 3 locations
50; CHECK-NEXT:   .short  3
51; Loc 0: Register
52; CHECK-NEXT:   .byte 1
53; CHECK-NEXT:   .byte 0
54; CHECK-NEXT:   .short 4
55; CHECK-NEXT:   .short {{[0-9]+}}
56; CHECK-NEXT:   .short 0
57; CHECK-NEXT:   .long 0
58; Loc 1: Register
59; CHECK-NEXT:   .byte 1
60; CHECK-NEXT:   .byte 0
61; CHECK-NEXT:   .short 4
62; CHECK-NEXT:   .short {{[0-9]+}}
63; CHECK-NEXT:   .short 0
64; CHECK-NEXT:   .long 0
65; Loc 2: Constant 3
66; CHECK-NEXT:   .byte 4
67; CHECK-NEXT:   .byte 0
68; CHECK-NEXT:   .short 8
69; CHECK-NEXT:   .short  0
70; CHECK-NEXT:   .short 0
71; CHECK-NEXT:   .long 3
72define i64 @test() nounwind ssp uwtable {
73entry:
74  call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 14, i8* null, i32 2, i32 1, i32 2, i64 3)
75  ret i64 0
76}
77
78; property access 1 - %obj is an anyreg call argument and should therefore be in a register
79; CHECK:        .long   .L{{.*}}-property_access1
80; CHECK-NEXT:   .short  0
81; 2 locations
82; CHECK-NEXT:   .short  2
83; Loc 0: Register <-- this is the return register
84; CHECK-NEXT:   .byte 1
85; CHECK-NEXT:   .byte 0
86; CHECK-NEXT:   .short 8
87; CHECK-NEXT:   .short {{[0-9]+}}
88; CHECK-NEXT:   .short 0
89; CHECK-NEXT:   .long 0
90; Loc 1: Register
91; CHECK-NEXT:   .byte 1
92; CHECK-NEXT:   .byte 0
93; CHECK-NEXT:   .short 8
94; CHECK-NEXT:   .short {{[0-9]+}}
95; CHECK-NEXT:   .short 0
96; CHECK-NEXT:   .long 0
97define i64 @property_access1(i8* %obj) nounwind ssp uwtable {
98entry:
99  %f = inttoptr i64 12297829382473034410 to i8*
100  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 14, i8* %f, i32 1, i8* %obj)
101  ret i64 %ret
102}
103
104; property access 2 - %obj is an anyreg call argument and should therefore be in a register
105; CHECK:        .long   .L{{.*}}-property_access2
106; CHECK-NEXT:   .short  0
107; 2 locations
108; CHECK-NEXT:   .short  2
109; Loc 0: Register <-- this is the return register
110; CHECK-NEXT:   .byte 1
111; CHECK-NEXT:   .byte 0
112; CHECK-NEXT:   .short 8
113; CHECK-NEXT:   .short {{[0-9]+}}
114; CHECK-NEXT:   .short 0
115; CHECK-NEXT:   .long 0
116; Loc 1: Register
117; CHECK-NEXT:   .byte 1
118; CHECK-NEXT:   .byte 0
119; CHECK-NEXT:   .short 8
120; CHECK-NEXT:   .short {{[0-9]+}}
121; CHECK-NEXT:   .short 0
122; CHECK-NEXT:   .long 0
123define i64 @property_access2() nounwind ssp uwtable {
124entry:
125  %obj = alloca i64, align 8
126  %f = inttoptr i64 12297829382473034410 to i8*
127  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 14, i8* %f, i32 1, i64* %obj)
128  ret i64 %ret
129}
130
131; property access 3 - %obj is a frame index
132; CHECK:        .long   .L{{.*}}-property_access3
133; CHECK-NEXT:   .short  0
134; 2 locations
135; CHECK-NEXT:   .short  2
136; Loc 0: Register <-- this is the return register
137; CHECK-NEXT:   .byte 1
138; CHECK-NEXT:   .byte 0
139; CHECK-NEXT:   .short 8
140; CHECK-NEXT:   .short {{[0-9]+}}
141; CHECK-NEXT:   .short 0
142; CHECK-NEXT:   .long 0
143; Loc 1: Direct %r15 + 160
144; CHECK-NEXT:   .byte 2
145; CHECK-NEXT:   .byte 0
146; CHECK-NEXT:   .short 8
147; CHECK-NEXT:   .short 15
148; CHECK-NEXT:   .short 0
149; CHECK-NEXT:   .long  160
150define i64 @property_access3() nounwind ssp uwtable {
151entry:
152  %obj = alloca i64, align 8
153  %f = inttoptr i64 12297829382473034410 to i8*
154  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 14, i8* %f, i32 0, i64* %obj)
155  ret i64 %ret
156}
157
158; anyreg_test1
159; CHECK:        .long   .L{{.*}}-anyreg_test1
160; CHECK-NEXT:   .short  0
161; 13 locations
162; CHECK-NEXT:   .short  13
163; Loc 0: Register <-- this is the return register
164; CHECK-NEXT:   .byte 1
165; CHECK-NEXT:   .byte 0
166; CHECK-NEXT:   .short 8
167; CHECK-NEXT:   .short {{[0-9]+}}
168; CHECK-NEXT:   .short 0
169; CHECK-NEXT:   .long 0
170; Loc 1: Register
171; CHECK-NEXT:   .byte 1
172; CHECK-NEXT:   .byte 0
173; CHECK-NEXT:   .short 8
174; CHECK-NEXT:   .short {{[0-9]+}}
175; CHECK-NEXT:   .short 0
176; CHECK-NEXT:   .long 0
177; Loc 2: Register
178; CHECK-NEXT:   .byte 1
179; CHECK-NEXT:   .byte 0
180; CHECK-NEXT:   .short 8
181; CHECK-NEXT:   .short {{[0-9]+}}
182; CHECK-NEXT:   .short 0
183; CHECK-NEXT:   .long 0
184; Loc 3: Register
185; CHECK-NEXT:   .byte 1
186; CHECK-NEXT:   .byte 0
187; CHECK-NEXT:   .short 8
188; CHECK-NEXT:   .short {{[0-9]+}}
189; CHECK-NEXT:   .short 0
190; CHECK-NEXT:   .long 0
191; Loc 4: Register
192; CHECK-NEXT:   .byte 1
193; CHECK-NEXT:   .byte 0
194; CHECK-NEXT:   .short 8
195; CHECK-NEXT:   .short {{[0-9]+}}
196; CHECK-NEXT:   .short 0
197; CHECK-NEXT:   .long 0
198; Loc 5: Register
199; CHECK-NEXT:   .byte 1
200; CHECK-NEXT:   .byte 0
201; CHECK-NEXT:   .short 8
202; CHECK-NEXT:   .short {{[0-9]+}}
203; CHECK-NEXT:   .short 0
204; CHECK-NEXT:   .long 0
205; Loc 6: Register
206; CHECK-NEXT:   .byte 1
207; CHECK-NEXT:   .byte 0
208; CHECK-NEXT:   .short 8
209; CHECK-NEXT:   .short {{[0-9]+}}
210; CHECK-NEXT:   .short 0
211; CHECK-NEXT:   .long 0
212; Loc 7: Register
213; CHECK-NEXT:   .byte 1
214; CHECK-NEXT:   .byte 0
215; CHECK-NEXT:   .short 8
216; CHECK-NEXT:   .short {{[0-9]+}}
217; CHECK-NEXT:   .short 0
218; CHECK-NEXT:   .long 0
219; Loc 8: Register
220; CHECK-NEXT:   .byte 1
221; CHECK-NEXT:   .byte 0
222; CHECK-NEXT:   .short 8
223; CHECK-NEXT:   .short {{[0-9]+}}
224; CHECK-NEXT:   .short 0
225; CHECK-NEXT:   .long 0
226; Loc 9: Register
227; CHECK-NEXT:   .byte 1
228; CHECK-NEXT:   .byte 0
229; CHECK-NEXT:   .short 8
230; CHECK-NEXT:   .short {{[0-9]+}}
231; CHECK-NEXT:   .short 0
232; CHECK-NEXT:   .long 0
233; Loc 10: Register
234; CHECK-NEXT:   .byte 1
235; CHECK-NEXT:   .byte 0
236; CHECK-NEXT:   .short 8
237; CHECK-NEXT:   .short {{[0-9]+}}
238; CHECK-NEXT:   .short 0
239; CHECK-NEXT:   .long 0
240; Loc 11: Register
241; CHECK-NEXT:   .byte 1
242; CHECK-NEXT:   .byte 0
243; CHECK-NEXT:   .short 8
244; CHECK-NEXT:   .short {{[0-9]+}}
245; CHECK-NEXT:   .short 0
246; CHECK-NEXT:   .long 0
247; Loc 12: Register
248; CHECK-NEXT:   .byte 1
249; CHECK-NEXT:   .byte 0
250; CHECK-NEXT:   .short 8
251; CHECK-NEXT:   .short {{[0-9]+}}
252; CHECK-NEXT:   .short 0
253; CHECK-NEXT:   .long 0
254define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
255entry:
256  %f = inttoptr i64 12297829382473034410 to i8*
257  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 14, i8* %f, i32 12, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
258  ret i64 %ret
259}
260
261; anyreg_test2
262; CHECK:        .long   .L{{.*}}-anyreg_test2
263; CHECK-NEXT:   .short  0
264; 13 locations
265; CHECK-NEXT:   .short  13
266; Loc 0: Register <-- this is the return register
267; CHECK-NEXT:   .byte 1
268; CHECK-NEXT:   .byte 0
269; CHECK-NEXT:   .short 8
270; CHECK-NEXT:   .short {{[0-9]+}}
271; CHECK-NEXT:   .short 0
272; CHECK-NEXT:   .long 0
273; Loc 1: Register
274; CHECK-NEXT:   .byte 1
275; CHECK-NEXT:   .byte 0
276; CHECK-NEXT:   .short 8
277; CHECK-NEXT:   .short {{[0-9]+}}
278; CHECK-NEXT:   .short 0
279; CHECK-NEXT:   .long 0
280; Loc 2: Register
281; CHECK-NEXT:   .byte 1
282; CHECK-NEXT:   .byte 0
283; CHECK-NEXT:   .short 8
284; CHECK-NEXT:   .short {{[0-9]+}}
285; CHECK-NEXT:   .short 0
286; CHECK-NEXT:   .long 0
287; Loc 3: Register
288; CHECK-NEXT:   .byte 1
289; CHECK-NEXT:   .byte 0
290; CHECK-NEXT:   .short 8
291; CHECK-NEXT:   .short {{[0-9]+}}
292; CHECK-NEXT:   .short 0
293; CHECK-NEXT:   .long 0
294; Loc 4: Register
295; CHECK-NEXT:   .byte 1
296; CHECK-NEXT:   .byte 0
297; CHECK-NEXT:   .short 8
298; CHECK-NEXT:   .short {{[0-9]+}}
299; CHECK-NEXT:   .short 0
300; CHECK-NEXT:   .long 0
301; Loc 5: Register
302; CHECK-NEXT:   .byte 1
303; CHECK-NEXT:   .byte 0
304; CHECK-NEXT:   .short 8
305; CHECK-NEXT:   .short {{[0-9]+}}
306; CHECK-NEXT:   .short 0
307; CHECK-NEXT:   .long 0
308; Loc 6: Register
309; CHECK-NEXT:   .byte 1
310; CHECK-NEXT:   .byte 0
311; CHECK-NEXT:   .short 8
312; CHECK-NEXT:   .short {{[0-9]+}}
313; CHECK-NEXT:   .short 0
314; CHECK-NEXT:   .long 0
315; Loc 7: Register
316; CHECK-NEXT:   .byte 1
317; CHECK-NEXT:   .byte 0
318; CHECK-NEXT:   .short 8
319; CHECK-NEXT:   .short {{[0-9]+}}
320; CHECK-NEXT:   .short 0
321; CHECK-NEXT:   .long 0
322; Loc 8: Register
323; CHECK-NEXT:   .byte 1
324; CHECK-NEXT:   .byte 0
325; CHECK-NEXT:   .short 8
326; CHECK-NEXT:   .short {{[0-9]+}}
327; CHECK-NEXT:   .short 0
328; CHECK-NEXT:   .long 0
329; Loc 9: Register
330; CHECK-NEXT:   .byte 1
331; CHECK-NEXT:   .byte 0
332; CHECK-NEXT:   .short 8
333; CHECK-NEXT:   .short {{[0-9]+}}
334; CHECK-NEXT:   .short 0
335; CHECK-NEXT:   .long 0
336; Loc 10: Register
337; CHECK-NEXT:   .byte 1
338; CHECK-NEXT:   .byte 0
339; CHECK-NEXT:   .short 8
340; CHECK-NEXT:   .short {{[0-9]+}}
341; CHECK-NEXT:   .short 0
342; CHECK-NEXT:   .long 0
343; Loc 11: Register
344; CHECK-NEXT:   .byte 1
345; CHECK-NEXT:   .byte 0
346; CHECK-NEXT:   .short 8
347; CHECK-NEXT:   .short {{[0-9]+}}
348; CHECK-NEXT:   .short 0
349; CHECK-NEXT:   .long 0
350; Loc 12: Register
351; CHECK-NEXT:   .byte 1
352; CHECK-NEXT:   .byte 0
353; CHECK-NEXT:   .short 8
354; CHECK-NEXT:   .short {{[0-9]+}}
355; CHECK-NEXT:   .short 0
356; CHECK-NEXT:   .long 0
357define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12) nounwind ssp uwtable {
358entry:
359  %f = inttoptr i64 12297829382473034410 to i8*
360  %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 14, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12)
361  ret i64 %ret
362}
363
364; Test spilling the return value of an anyregcc call.
365;
366; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
367;
368; CHECK:      .long  .L{{.*}}-patchpoint_spilldef
369; CHECK-NEXT: .short 0
370; CHECK-NEXT: .short 3
371; Loc 0: Register (some register that will be spilled to the stack)
372; CHECK-NEXT: .byte  1
373; CHECK-NEXT: .byte  0
374; CHECK-NEXT: .short  8
375; CHECK-NEXT: .short {{[0-9]+}}
376; CHECK-NEXT: .short 0
377; CHECK-NEXT: .long  0
378; Loc 1: Register %r2
379; CHECK-NEXT: .byte  1
380; CHECK-NEXT: .byte  0
381; CHECK-NEXT: .short  8
382; CHECK-NEXT: .short 2
383; CHECK-NEXT: .short 0
384; CHECK-NEXT: .long  0
385; Loc 1: Register %r3
386; CHECK-NEXT: .byte  1
387; CHECK-NEXT: .byte  0
388; CHECK-NEXT: .short  8
389; CHECK-NEXT: .short 3
390; CHECK-NEXT: .short 0
391; CHECK-NEXT: .long  0
392define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
393entry:
394  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
395  tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
396  ret i64 %result
397}
398
399; Test spilling the arguments of an anyregcc call.
400;
401; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled
402;
403; CHECK:      .long .L{{.*}}-patchpoint_spillargs
404; CHECK-NEXT: .short 0
405; CHECK-NEXT: .short 5
406; Loc 0: Return a register
407; CHECK-NEXT: .byte  1
408; CHECK-NEXT: .byte  0
409; CHECK-NEXT: .short  8
410; CHECK-NEXT: .short {{[0-9]+}}
411; CHECK-NEXT: .short 0
412; CHECK-NEXT: .long  0
413; Loc 1: Arg0 in a Register
414; CHECK-NEXT: .byte  1
415; CHECK-NEXT: .byte  0
416; CHECK-NEXT: .short  8
417; CHECK-NEXT: .short {{[0-9]+}}
418; CHECK-NEXT: .short 0
419; CHECK-NEXT: .long  0
420; Loc 2: Arg1 in a Register
421; CHECK-NEXT: .byte  1
422; CHECK-NEXT: .byte  0
423; CHECK-NEXT: .short  8
424; CHECK-NEXT: .short {{[0-9]+}}
425; CHECK-NEXT: .short 0
426; CHECK-NEXT: .long  0
427; Loc 3: Arg2 spilled to %r15 +
428; CHECK-NEXT: .byte  3
429; CHECK-NEXT: .byte  0
430; CHECK-NEXT: .short  8
431; CHECK-NEXT: .short 15
432; CHECK-NEXT: .short 0
433; CHECK-NEXT: .long
434; Loc 4: Arg3 spilled to %r15 +
435; CHECK-NEXT: .byte  3
436; CHECK-NEXT: .byte  0
437; CHECK-NEXT: .short  8
438; CHECK-NEXT: .short 15
439; CHECK-NEXT: .short 0
440; CHECK-NEXT: .long
441define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
442entry:
443  tail call void asm sideeffect "nopr %r0", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14}"() nounwind
444  %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 14, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
445  ret i64 %result
446}
447
448declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
449declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
450