1; Test the vector constraint "v" and explicit vector register names. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -no-integrated-as | FileCheck %s 4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -no-integrated-as | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-Z14 5 6define float @f1() { 7; CHECK-LABEL: f1: 8; CHECK: lzer %f1 9; CHECK: blah %f0 %f1 10; CHECK: br %r14 11 %val = call float asm "blah $0 $1", "=&v,v" (float 0.0) 12 ret float %val 13} 14 15define double @f2() { 16; CHECK-LABEL: f2: 17; CHECK: lzdr %f1 18; CHECK: blah %f0 %f1 19; CHECK: br %r14 20 %val = call double asm "blah $0 $1", "=&v,v" (double 0.0) 21 ret double %val 22} 23 24define fp128 @f3() { 25; CHECK-LABEL: f3: 26; CHECK-Z14: vzero %v0 27; CHECK: blah %v1 %v0 28; CHECK: vst %v1, 0(%r2) 29; CHECK: br %r14 30 %val = call fp128 asm "blah $0 $1", "=&v,v" (fp128 0xL00000000000000000000000000000000) 31 ret fp128 %val 32} 33 34define <2 x i64> @f4() { 35; CHECK-LABEL: f4: 36; CHECK: vrepig %v0, 1 37; CHECK: blah %v24 %v0 38; CHECK: br %r14 39 %val = call <2 x i64> asm "blah $0 $1", "=&v,v" (<2 x i64> <i64 1, i64 1>) 40 ret <2 x i64> %val 41} 42 43define <4 x i32> @f5() { 44; CHECK-LABEL: f5: 45; CHECK: vrepif %v0, 1 46; CHECK: blah %v24 %v0 47; CHECK: br %r14 48 %val = call <4 x i32> asm "blah $0 $1", "=&v,v" (<4 x i32> <i32 1, i32 1, i32 1, i32 1>) 49 ret <4 x i32> %val 50} 51 52define <8 x i16> @f6() { 53; CHECK-LABEL: f6: 54; CHECK: vrepih %v0, 1 55; CHECK: blah %v24 %v0 56; CHECK: br %r14 57 %val = call <8 x i16> asm "blah $0 $1", "=&v,v" (<8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) 58 ret <8 x i16> %val 59} 60 61define <16 x i8> @f7() { 62; CHECK-LABEL: f7: 63; CHECK: vrepib %v0, 1 64; CHECK: blah %v24 %v0 65; CHECK: br %r14 66 %val = call <16 x i8> asm "blah $0 $1", "=&v,v" (<16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, 67 i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>) 68 ret <16 x i8> %val 69} 70 71define <2 x double> @f8() { 72; CHECK-LABEL: f8: 73; CHECK: vgbm %v0, 0 74; CHECK: blah %v24 %v0 75; CHECK: br %r14 76 %val = call <2 x double> asm "blah $0 $1", "=&v,v" (<2 x double> <double 0.0, double 0.0>) 77 ret <2 x double> %val 78} 79 80define <4 x float> @f9() { 81; CHECK-LABEL: f9: 82; CHECK: vgbm %v0, 0 83; CHECK: blah %v24 %v0 84; CHECK: br %r14 85 %val = call <4 x float> asm "blah $0 $1", "=&v,v" (<4 x float> <float 0.0, float 0.0, float 0.0, float 0.0>) 86 ret <4 x float> %val 87} 88 89define float @f10() { 90; CHECK-LABEL: f10: 91; CHECK: lzer %f4 92; CHECK: blah %f4 93; CHECK: ldr %f0, %f4 94; CHECK: br %r14 95 %ret = call float asm "blah $0", "={v4},0" (float 0.0) 96 ret float %ret 97} 98 99define double @f11() { 100; CHECK-LABEL: f11: 101; CHECK: lzdr %f4 102; CHECK: blah %f4 103; CHECK: ldr %f0, %f4 104; CHECK: br %r14 105 %ret = call double asm "blah $0", "={v4},0" (double 0.0) 106 ret double %ret 107} 108 109define fp128 @f12() { 110; CHECK-LABEL: f12: 111; CHECK-Z14: vzero %v4 112; CHECK: blah %v4 113; CHECK: vst %v4, 0(%r2) 114; CHECK: br %r14 115 %ret = call fp128 asm "blah $0", "={v4},0" (fp128 0xL00000000000000000000000000000000) 116 ret fp128 %ret 117} 118 119define <2 x i64> @f13() { 120; CHECK-LABEL: f13: 121; CHECK: vrepig %v4, 1 122; CHECK: blah %v4 123; CHECK: vlr %v24, %v4 124; CHECK: br %r14 125 %ret = call <2 x i64> asm "blah $0", "={v4},0" (<2 x i64> <i64 1, i64 1>) 126 ret <2 x i64> %ret 127} 128 129define <2 x i64> @f14(<2 x i64> %in) { 130; CHECK-LABEL: f14: 131; CHECK: vlr [[REG:%v[0-9]+]], %v24 132; CHECK: blah 133; CHECK: vlr %v24, [[REG]] 134; CHECK: br %r14 135 call void asm sideeffect "blah", "~{v24},~{cc}"() 136 ret <2 x i64> %in 137} 138 139