1; Test 64-bit signed comparison in which the second operand is sign-extended 2; from an i16 memory value. 3; 4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 5 6; Check CGH with no displacement. 7define void @f1(i64 %lhs, i16 *%src, i64 *%dst) { 8; CHECK-LABEL: f1: 9; CHECK: cgh %r2, 0(%r3) 10; CHECK: br %r14 11 %half = load i16, i16 *%src 12 %rhs = sext i16 %half to i64 13 %cond = icmp slt i64 %lhs, %rhs 14 %res = select i1 %cond, i64 100, i64 200 15 store i64 %res, i64 *%dst 16 ret void 17} 18 19; Check the high end of the aligned CGH range. 20define void @f2(i64 %lhs, i16 *%src, i64 *%dst) { 21; CHECK-LABEL: f2: 22; CHECK: cgh %r2, 524286(%r3) 23; CHECK: br %r14 24 %ptr = getelementptr i16, i16 *%src, i64 262143 25 %half = load i16, i16 *%ptr 26 %rhs = sext i16 %half to i64 27 %cond = icmp slt i64 %lhs, %rhs 28 %res = select i1 %cond, i64 100, i64 200 29 store i64 %res, i64 *%dst 30 ret void 31} 32 33; Check the next halfword up, which needs separate address logic. 34; Other sequences besides this one would be OK. 35define void @f3(i64 %lhs, i16 *%src, i64 *%dst) { 36; CHECK-LABEL: f3: 37; CHECK: agfi %r3, 524288 38; CHECK: cgh %r2, 0(%r3) 39; CHECK: br %r14 40 %ptr = getelementptr i16, i16 *%src, i64 262144 41 %half = load i16, i16 *%ptr 42 %rhs = sext i16 %half to i64 43 %cond = icmp slt i64 %lhs, %rhs 44 %res = select i1 %cond, i64 100, i64 200 45 store i64 %res, i64 *%dst 46 ret void 47} 48 49; Check the high end of the negative aligned CGH range. 50define void @f4(i64 %lhs, i16 *%src, i64 *%dst) { 51; CHECK-LABEL: f4: 52; CHECK: cgh %r2, -2(%r3) 53; CHECK: br %r14 54 %ptr = getelementptr i16, i16 *%src, i64 -1 55 %half = load i16, i16 *%ptr 56 %rhs = sext i16 %half to i64 57 %cond = icmp slt i64 %lhs, %rhs 58 %res = select i1 %cond, i64 100, i64 200 59 store i64 %res, i64 *%dst 60 ret void 61} 62 63; Check the low end of the CGH range. 64define void @f5(i64 %lhs, i16 *%src, i64 *%dst) { 65; CHECK-LABEL: f5: 66; CHECK: cgh %r2, -524288(%r3) 67; CHECK: br %r14 68 %ptr = getelementptr i16, i16 *%src, i64 -262144 69 %half = load i16, i16 *%ptr 70 %rhs = sext i16 %half to i64 71 %cond = icmp slt i64 %lhs, %rhs 72 %res = select i1 %cond, i64 100, i64 200 73 store i64 %res, i64 *%dst 74 ret void 75} 76 77; Check the next halfword down, which needs separate address logic. 78; Other sequences besides this one would be OK. 79define void @f6(i64 %lhs, i16 *%src, i64 *%dst) { 80; CHECK-LABEL: f6: 81; CHECK: agfi %r3, -524290 82; CHECK: cgh %r2, 0(%r3) 83; CHECK: br %r14 84 %ptr = getelementptr i16, i16 *%src, i64 -262145 85 %half = load i16, i16 *%ptr 86 %rhs = sext i16 %half to i64 87 %cond = icmp slt i64 %lhs, %rhs 88 %res = select i1 %cond, i64 100, i64 200 89 store i64 %res, i64 *%dst 90 ret void 91} 92 93; Check that CGH allows an index. 94define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) { 95; CHECK-LABEL: f7: 96; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}}) 97; CHECK: br %r14 98 %add1 = add i64 %base, %index 99 %add2 = add i64 %add1, 4096 100 %ptr = inttoptr i64 %add2 to i16 * 101 %half = load i16, i16 *%ptr 102 %rhs = sext i16 %half to i64 103 %cond = icmp slt i64 %lhs, %rhs 104 %res = select i1 %cond, i64 100, i64 200 105 store i64 %res, i64 *%dst 106 ret void 107} 108 109; Check the comparison can be reversed if that allows CGH to be used. 110define double @f8(double %a, double %b, i64 %rhs, i16 *%src) { 111; CHECK-LABEL: f8: 112; CHECK: cgh %r2, 0(%r3) 113; CHECK-NEXT: bhr %r14 114; CHECK: ldr %f0, %f2 115; CHECK: br %r14 116 %half = load i16, i16 *%src 117 %lhs = sext i16 %half to i64 118 %cond = icmp slt i64 %lhs, %rhs 119 %res = select i1 %cond, double %a, double %b 120 ret double %res 121} 122