1; Test zero extensions from an i32 to an i64. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Test register extension, starting with an i32. 6define i64 @f1(i32 %a) { 7; CHECK-LABEL: f1: 8; CHECK: llgfr %r2, %r2 9; CHECK: br %r14 10 %ext = zext i32 %a to i64 11 ret i64 %ext 12} 13 14; ...and again with an i64. 15define i64 @f2(i64 %a) { 16; CHECK-LABEL: f2: 17; CHECK: llgfr %r2, %r2 18; CHECK: br %r14 19 %word = trunc i64 %a to i32 20 %ext = zext i32 %word to i64 21 ret i64 %ext 22} 23 24; Check ANDs that are equivalent to zero extension. 25define i64 @f3(i64 %a) { 26; CHECK-LABEL: f3: 27; CHECK: llgfr %r2, %r2 28; CHECK: br %r14 29 %ext = and i64 %a, 4294967295 30 ret i64 %ext 31} 32 33; Check LLGF with no displacement. 34define i64 @f4(i32 *%src) { 35; CHECK-LABEL: f4: 36; CHECK: llgf %r2, 0(%r2) 37; CHECK: br %r14 38 %word = load i32, i32 *%src 39 %ext = zext i32 %word to i64 40 ret i64 %ext 41} 42 43; Check the high end of the LLGF range. 44define i64 @f5(i32 *%src) { 45; CHECK-LABEL: f5: 46; CHECK: llgf %r2, 524284(%r2) 47; CHECK: br %r14 48 %ptr = getelementptr i32, i32 *%src, i64 131071 49 %word = load i32, i32 *%ptr 50 %ext = zext i32 %word to i64 51 ret i64 %ext 52} 53 54; Check the next word up, which needs separate address logic. 55; Other sequences besides this one would be OK. 56define i64 @f6(i32 *%src) { 57; CHECK-LABEL: f6: 58; CHECK: agfi %r2, 524288 59; CHECK: llgf %r2, 0(%r2) 60; CHECK: br %r14 61 %ptr = getelementptr i32, i32 *%src, i64 131072 62 %word = load i32, i32 *%ptr 63 %ext = zext i32 %word to i64 64 ret i64 %ext 65} 66 67; Check the high end of the negative LLGF range. 68define i64 @f7(i32 *%src) { 69; CHECK-LABEL: f7: 70; CHECK: llgf %r2, -4(%r2) 71; CHECK: br %r14 72 %ptr = getelementptr i32, i32 *%src, i64 -1 73 %word = load i32, i32 *%ptr 74 %ext = zext i32 %word to i64 75 ret i64 %ext 76} 77 78; Check the low end of the LLGF range. 79define i64 @f8(i32 *%src) { 80; CHECK-LABEL: f8: 81; CHECK: llgf %r2, -524288(%r2) 82; CHECK: br %r14 83 %ptr = getelementptr i32, i32 *%src, i64 -131072 84 %word = load i32, i32 *%ptr 85 %ext = zext i32 %word to i64 86 ret i64 %ext 87} 88 89; Check the next word down, which needs separate address logic. 90; Other sequences besides this one would be OK. 91define i64 @f9(i32 *%src) { 92; CHECK-LABEL: f9: 93; CHECK: agfi %r2, -524292 94; CHECK: llgf %r2, 0(%r2) 95; CHECK: br %r14 96 %ptr = getelementptr i32, i32 *%src, i64 -131073 97 %word = load i32, i32 *%ptr 98 %ext = zext i32 %word to i64 99 ret i64 %ext 100} 101 102; Check that LLGF allows an index. 103define i64 @f10(i64 %src, i64 %index) { 104; CHECK-LABEL: f10: 105; CHECK: llgf %r2, 524287(%r3,%r2) 106; CHECK: br %r14 107 %add1 = add i64 %src, %index 108 %add2 = add i64 %add1, 524287 109 %ptr = inttoptr i64 %add2 to i32 * 110 %word = load i32, i32 *%ptr 111 %ext = zext i32 %word to i64 112 ret i64 %ext 113} 114