1; Test 32-bit GPR stores. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Test an i32 store. 6define void @f1(i32 *%dst, i32 %val) { 7; CHECK-LABEL: f1: 8; CHECK: st %r3, 0(%r2) 9; CHECK: br %r14 10 store i32 %val, i32 *%dst 11 ret void 12} 13 14; Test a truncating i64 store. 15define void @f2(i32 *%dst, i64 %val) { 16 %word = trunc i64 %val to i32 17 store i32 %word, i32 *%dst 18 ret void 19} 20 21; Check the high end of the aligned ST range. 22define void @f3(i32 *%dst, i32 %val) { 23; CHECK-LABEL: f3: 24; CHECK: st %r3, 4092(%r2) 25; CHECK: br %r14 26 %ptr = getelementptr i32, i32 *%dst, i64 1023 27 store i32 %val, i32 *%ptr 28 ret void 29} 30 31; Check the next word up, which should use STY instead of ST. 32define void @f4(i32 *%dst, i32 %val) { 33; CHECK-LABEL: f4: 34; CHECK: sty %r3, 4096(%r2) 35; CHECK: br %r14 36 %ptr = getelementptr i32, i32 *%dst, i64 1024 37 store i32 %val, i32 *%ptr 38 ret void 39} 40 41; Check the high end of the aligned STY range. 42define void @f5(i32 *%dst, i32 %val) { 43; CHECK-LABEL: f5: 44; CHECK: sty %r3, 524284(%r2) 45; CHECK: br %r14 46 %ptr = getelementptr i32, i32 *%dst, i64 131071 47 store i32 %val, i32 *%ptr 48 ret void 49} 50 51; Check the next word up, which needs separate address logic. 52; Other sequences besides this one would be OK. 53define void @f6(i32 *%dst, i32 %val) { 54; CHECK-LABEL: f6: 55; CHECK: agfi %r2, 524288 56; CHECK: st %r3, 0(%r2) 57; CHECK: br %r14 58 %ptr = getelementptr i32, i32 *%dst, i64 131072 59 store i32 %val, i32 *%ptr 60 ret void 61} 62 63; Check the high end of the negative aligned STY range. 64define void @f7(i32 *%dst, i32 %val) { 65; CHECK-LABEL: f7: 66; CHECK: sty %r3, -4(%r2) 67; CHECK: br %r14 68 %ptr = getelementptr i32, i32 *%dst, i64 -1 69 store i32 %val, i32 *%ptr 70 ret void 71} 72 73; Check the low end of the STY range. 74define void @f8(i32 *%dst, i32 %val) { 75; CHECK-LABEL: f8: 76; CHECK: sty %r3, -524288(%r2) 77; CHECK: br %r14 78 %ptr = getelementptr i32, i32 *%dst, i64 -131072 79 store i32 %val, i32 *%ptr 80 ret void 81} 82 83; Check the next word down, which needs separate address logic. 84; Other sequences besides this one would be OK. 85define void @f9(i32 *%dst, i32 %val) { 86; CHECK-LABEL: f9: 87; CHECK: agfi %r2, -524292 88; CHECK: st %r3, 0(%r2) 89; CHECK: br %r14 90 %ptr = getelementptr i32, i32 *%dst, i64 -131073 91 store i32 %val, i32 *%ptr 92 ret void 93} 94 95; Check that ST allows an index. 96define void @f10(i64 %dst, i64 %index, i32 %val) { 97; CHECK-LABEL: f10: 98; CHECK: st %r4, 4095(%r3,%r2) 99; CHECK: br %r14 100 %add1 = add i64 %dst, %index 101 %add2 = add i64 %add1, 4095 102 %ptr = inttoptr i64 %add2 to i32 * 103 store i32 %val, i32 *%ptr 104 ret void 105} 106 107; Check that STY allows an index. 108define void @f11(i64 %dst, i64 %index, i32 %val) { 109; CHECK-LABEL: f11: 110; CHECK: sty %r4, 4096(%r3,%r2) 111; CHECK: br %r14 112 %add1 = add i64 %dst, %index 113 %add2 = add i64 %add1, 4096 114 %ptr = inttoptr i64 %add2 to i32 * 115 store i32 %val, i32 *%ptr 116 ret void 117} 118