1; Test sequences that can use RXSBG. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Test the simple case. 6define i32 @f1(i32 %a, i32 %b) { 7; CHECK-LABEL: f1: 8; CHECK: rxsbg %r2, %r3, 59, 59, 0 9; CHECK: br %r14 10 %andb = and i32 %b, 16 11 %xor = xor i32 %a, %andb 12 ret i32 %xor 13} 14 15; ...and again with i64. 16define i64 @f2(i64 %a, i64 %b) { 17; CHECK-LABEL: f2: 18; CHECK: rxsbg %r2, %r3, 59, 59, 0 19; CHECK: br %r14 20 %andb = and i64 %b, 16 21 %xor = xor i64 %a, %andb 22 ret i64 %xor 23} 24 25; Test a case where wraparound is needed. 26define i32 @f3(i32 %a, i32 %b) { 27; CHECK-LABEL: f3: 28; CHECK: rxsbg %r2, %r3, 63, 60, 0 29; CHECK: br %r14 30 %andb = and i32 %b, -7 31 %xor = xor i32 %a, %andb 32 ret i32 %xor 33} 34 35; ...and again with i64. 36define i64 @f4(i64 %a, i64 %b) { 37; CHECK-LABEL: f4: 38; CHECK: rxsbg %r2, %r3, 63, 60, 0 39; CHECK: br %r14 40 %andb = and i64 %b, -7 41 %xor = xor i64 %a, %andb 42 ret i64 %xor 43} 44 45; Test a case with just a shift. 46define i32 @f6(i32 %a, i32 %b) { 47; CHECK-LABEL: f6: 48; CHECK: rxsbg %r2, %r3, 32, 51, 12 49; CHECK: br %r14 50 %shlb = shl i32 %b, 12 51 %xor = xor i32 %a, %shlb 52 ret i32 %xor 53} 54 55; ...and again with i64. 56define i64 @f7(i64 %a, i64 %b) { 57; CHECK-LABEL: f7: 58; CHECK: rxsbg %r2, %r3, 0, 51, 12 59; CHECK: br %r14 60 %shlb = shl i64 %b, 12 61 %xor = xor i64 %a, %shlb 62 ret i64 %xor 63} 64 65; Test a case with just a rotate (using XOR for the rotate combination too, 66; to test that this kind of rotate does get recognised by the target- 67; independent code). This can't use RXSBG. 68define i32 @f8(i32 %a, i32 %b) { 69; CHECK-LABEL: f8: 70; CHECK: rll {{%r[0-5]}} 71; CHECK: xr {{%r[0-5]}} 72; CHECK: br %r14 73 %shlb = shl i32 %b, 30 74 %shrb = lshr i32 %b, 2 75 %rotlb = xor i32 %shlb, %shrb 76 %xor = xor i32 %a, %rotlb 77 ret i32 %xor 78} 79 80; ...and again with i64, which can use RXSBG for the rotate. 81define i64 @f9(i64 %a, i64 %b) { 82; CHECK-LABEL: f9: 83; CHECK: rxsbg %r2, %r3, 0, 63, 47 84; CHECK: br %r14 85 %shlb = shl i64 %b, 47 86 %shrb = lshr i64 %b, 17 87 %rotlb = xor i64 %shlb, %shrb 88 %xor = xor i64 %a, %rotlb 89 ret i64 %xor 90} 91 92; Test a case with a shift and AND. 93define i32 @f10(i32 %a, i32 %b) { 94; CHECK-LABEL: f10: 95; CHECK: rxsbg %r2, %r3, 56, 59, 4 96; CHECK: br %r14 97 %shlb = shl i32 %b, 4 98 %andb = and i32 %shlb, 240 99 %xor = xor i32 %a, %andb 100 ret i32 %xor 101} 102 103; ...and again with i64. 104define i64 @f11(i64 %a, i64 %b) { 105; CHECK-LABEL: f11: 106; CHECK: rxsbg %r2, %r3, 56, 59, 4 107; CHECK: br %r14 108 %shlb = shl i64 %b, 4 109 %andb = and i64 %shlb, 240 110 %xor = xor i64 %a, %andb 111 ret i64 %xor 112} 113 114; Check the handling of zext and XOR, which can use ROSBG. 115define i64 @f12(i64 %a, i32 %b) { 116; CHECK-LABEL: f12: 117; CHECK: rxsbg %r2, %r3, 32, 63, 0 118; CHECK: br %r14 119 %add = add i32 %b, 1 120 %ext = zext i32 %add to i64 121 %xor = xor i64 %a, %ext 122 ret i64 %xor 123} 124