1; Test SETCC with an i64 result for every floating-point condition. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s 4 5; Test CC in { 0 } 6define i64 @f1(float %a, float %b) { 7; CHECK-LABEL: f1: 8; CHECK: ipm [[REG:%r[0-5]]] 9; CHECK-NEXT: afi [[REG]], -268435456 10; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 11; CHECK: br %r14 12 %cond = fcmp oeq float %a, %b 13 %res = zext i1 %cond to i64 14 ret i64 %res 15} 16 17; Test CC in { 1 } 18define i64 @f2(float %a, float %b) { 19; CHECK-LABEL: f2: 20; CHECK: ipm [[REG:%r[0-5]]] 21; CHECK-NEXT: xilf [[REG]], 268435456 22; CHECK-NEXT: afi [[REG]], -268435456 23; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 24; CHECK: br %r14 25 %cond = fcmp olt float %a, %b 26 %res = zext i1 %cond to i64 27 ret i64 %res 28} 29 30; Test CC in { 0, 1 } 31define i64 @f3(float %a, float %b) { 32; CHECK-LABEL: f3: 33; CHECK: ipm [[REG:%r[0-5]]] 34; CHECK-NEXT: afi [[REG]], -536870912 35; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 36; CHECK: br %r14 37 %cond = fcmp ole float %a, %b 38 %res = zext i1 %cond to i64 39 ret i64 %res 40} 41 42; Test CC in { 2 } 43define i64 @f4(float %a, float %b) { 44; CHECK-LABEL: f4: 45; CHECK: ipm [[REG:%r[0-5]]] 46; CHECK-NEXT: xilf [[REG]], 268435456 47; CHECK-NEXT: afi [[REG]], 1342177280 48; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 49; CHECK: br %r14 50 %cond = fcmp ogt float %a, %b 51 %res = zext i1 %cond to i64 52 ret i64 %res 53} 54 55; Test CC in { 0, 2 } 56define i64 @f5(float %a, float %b) { 57; CHECK-LABEL: f5: 58; CHECK: ipm [[REG:%r[0-5]]] 59; CHECK-NEXT: xilf [[REG]], 4294967295 60; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36 61; CHECK: br %r14 62 %cond = fcmp oge float %a, %b 63 %res = zext i1 %cond to i64 64 ret i64 %res 65} 66 67; Test CC in { 1, 2 } 68define i64 @f6(float %a, float %b) { 69; CHECK-LABEL: f6: 70; CHECK: ipm [[REG:%r[0-5]]] 71; CHECK-NEXT: afi [[REG]], 268435456 72; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35 73; CHECK: br %r14 74 %cond = fcmp one float %a, %b 75 %res = zext i1 %cond to i64 76 ret i64 %res 77} 78 79; Test CC in { 0, 1, 2 } 80define i64 @f7(float %a, float %b) { 81; CHECK-LABEL: f7: 82; CHECK: ipm [[REG:%r[0-5]]] 83; CHECK-NEXT: afi [[REG]], -805306368 84; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 85; CHECK: br %r14 86 %cond = fcmp ord float %a, %b 87 %res = zext i1 %cond to i64 88 ret i64 %res 89} 90 91; Test CC in { 3 } 92define i64 @f8(float %a, float %b) { 93; CHECK-LABEL: f8: 94; CHECK: ipm [[REG:%r[0-5]]] 95; CHECK-NEXT: afi [[REG]], 1342177280 96; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 97; CHECK: br %r14 98 %cond = fcmp uno float %a, %b 99 %res = zext i1 %cond to i64 100 ret i64 %res 101} 102 103; Test CC in { 0, 3 } 104define i64 @f9(float %a, float %b) { 105; CHECK-LABEL: f9: 106; CHECK: ipm [[REG:%r[0-5]]] 107; CHECK-NEXT: afi [[REG]], -268435456 108; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35 109; CHECK: br %r14 110 %cond = fcmp ueq float %a, %b 111 %res = zext i1 %cond to i64 112 ret i64 %res 113} 114 115; Test CC in { 1, 3 } 116define i64 @f10(float %a, float %b) { 117; CHECK-LABEL: f10: 118; CHECK: ipm [[REG:%r[0-5]]] 119; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 36 120; CHECK: br %r14 121 %cond = fcmp ult float %a, %b 122 %res = zext i1 %cond to i64 123 ret i64 %res 124} 125 126; Test CC in { 0, 1, 3 } 127define i64 @f11(float %a, float %b) { 128; CHECK-LABEL: f11: 129; CHECK: ipm [[REG:%r[0-5]]] 130; CHECK-NEXT: xilf [[REG]], 268435456 131; CHECK-NEXT: afi [[REG]], -805306368 132; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 133; CHECK: br %r14 134 %cond = fcmp ule float %a, %b 135 %res = zext i1 %cond to i64 136 ret i64 %res 137} 138 139; Test CC in { 2, 3 } 140define i64 @f12(float %a, float %b) { 141; CHECK-LABEL: f12: 142; CHECK: ipm [[REG:%r[0-5]]] 143; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 35 144; CHECK: br %r14 145 %cond = fcmp ugt float %a, %b 146 %res = zext i1 %cond to i64 147 ret i64 %res 148} 149 150; Test CC in { 0, 2, 3 } 151define i64 @f13(float %a, float %b) { 152; CHECK-LABEL: f13: 153; CHECK: ipm [[REG:%r[0-5]]] 154; CHECK-NEXT: xilf [[REG]], 268435456 155; CHECK-NEXT: afi [[REG]], 1879048192 156; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 157; CHECK: br %r14 158 %cond = fcmp uge float %a, %b 159 %res = zext i1 %cond to i64 160 ret i64 %res 161} 162 163; Test CC in { 1, 2, 3 } 164define i64 @f14(float %a, float %b) { 165; CHECK-LABEL: f14: 166; CHECK: ipm [[REG:%r[0-5]]] 167; CHECK-NEXT: afi [[REG]], 1879048192 168; CHECK-NEXT: risbg %r2, [[REG]], 63, 191, 33 169; CHECK: br %r14 170 %cond = fcmp une float %a, %b 171 %res = zext i1 %cond to i64 172 ret i64 %res 173} 174