1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2 3 4--- | 5 define void @test_add_v16i8() { 6 %ret = add <16 x i8> undef, undef 7 ret void 8 } 9 10 define void @test_add_v8i16() { 11 %ret = add <8 x i16> undef, undef 12 ret void 13 } 14 15 define void @test_add_v4i32() { 16 %ret = add <4 x i32> undef, undef 17 ret void 18 } 19 20 define void @test_add_v2i64() { 21 %ret = add <2 x i64> undef, undef 22 ret void 23 } 24... 25--- 26name: test_add_v16i8 27alignment: 4 28legalized: false 29regBankSelected: false 30registers: 31 - { id: 0, class: _ } 32 - { id: 1, class: _ } 33 - { id: 2, class: _ } 34body: | 35 bb.1 (%ir-block.0): 36 liveins: $xmm0, $xmm1 37 38 ; ALL-LABEL: name: test_add_v16i8 39 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 40 ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 41 ; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]] 42 ; ALL: $xmm0 = COPY [[ADD]](<16 x s8>) 43 ; ALL: RET 0 44 %0(<16 x s8>) = IMPLICIT_DEF 45 %1(<16 x s8>) = IMPLICIT_DEF 46 %2(<16 x s8>) = G_ADD %0, %1 47 $xmm0 = COPY %2 48 RET 0 49 50... 51--- 52name: test_add_v8i16 53alignment: 4 54legalized: false 55regBankSelected: false 56registers: 57 - { id: 0, class: _ } 58 - { id: 1, class: _ } 59 - { id: 2, class: _ } 60body: | 61 bb.1 (%ir-block.0): 62 liveins: $xmm0, $xmm1 63 64 ; ALL-LABEL: name: test_add_v8i16 65 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 66 ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 67 ; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]] 68 ; ALL: $xmm0 = COPY [[ADD]](<8 x s16>) 69 ; ALL: RET 0 70 %0(<8 x s16>) = IMPLICIT_DEF 71 %1(<8 x s16>) = IMPLICIT_DEF 72 %2(<8 x s16>) = G_ADD %0, %1 73 $xmm0 = COPY %2 74 RET 0 75 76... 77--- 78name: test_add_v4i32 79alignment: 4 80legalized: false 81regBankSelected: false 82registers: 83 - { id: 0, class: _ } 84 - { id: 1, class: _ } 85 - { id: 2, class: _ } 86body: | 87 bb.1 (%ir-block.0): 88 liveins: $xmm0, $xmm1 89 90 ; ALL-LABEL: name: test_add_v4i32 91 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 92 ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 93 ; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]] 94 ; ALL: $xmm0 = COPY [[ADD]](<4 x s32>) 95 ; ALL: RET 0 96 %0(<4 x s32>) = IMPLICIT_DEF 97 %1(<4 x s32>) = IMPLICIT_DEF 98 %2(<4 x s32>) = G_ADD %0, %1 99 $xmm0 = COPY %2 100 RET 0 101 102... 103--- 104name: test_add_v2i64 105alignment: 4 106legalized: false 107regBankSelected: false 108registers: 109 - { id: 0, class: _ } 110 - { id: 1, class: _ } 111 - { id: 2, class: _ } 112body: | 113 bb.1 (%ir-block.0): 114 liveins: $xmm0, $xmm1 115 116 ; ALL-LABEL: name: test_add_v2i64 117 ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 118 ; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 119 ; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]] 120 ; ALL: $xmm0 = COPY [[ADD]](<2 x s64>) 121 ; ALL: RET 0 122 %0(<2 x s64>) = IMPLICIT_DEF 123 %1(<2 x s64>) = IMPLICIT_DEF 124 %2(<2 x s64>) = G_ADD %0, %1 125 $xmm0 = COPY %2 126 RET 0 127 128... 129