1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE2 3 4--- | 5 define void @test_sub_v16i8() { 6 %ret = sub <16 x i8> undef, undef 7 ret void 8 } 9 10 define void @test_sub_v8i16() { 11 %ret = sub <8 x i16> undef, undef 12 ret void 13 } 14 15 define void @test_sub_v4i32() { 16 %ret = sub <4 x i32> undef, undef 17 ret void 18 } 19 20 define void @test_sub_v2i64() { 21 %ret = sub <2 x i64> undef, undef 22 ret void 23 } 24... 25--- 26name: test_sub_v16i8 27alignment: 4 28legalized: false 29regBankSelected: false 30registers: 31 - { id: 0, class: _ } 32 - { id: 1, class: _ } 33 - { id: 2, class: _ } 34body: | 35 bb.1 (%ir-block.0): 36 liveins: $xmm0, $xmm1 37 38 ; ALL-LABEL: name: test_sub_v16i8 39 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 40 ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF 41 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s8>) = G_SUB [[DEF]], [[DEF1]] 42 ; ALL: RET 0 43 %0(<16 x s8>) = IMPLICIT_DEF 44 %1(<16 x s8>) = IMPLICIT_DEF 45 %2(<16 x s8>) = G_SUB %0, %1 46 $xmm0 = COPY %2 47 RET 0 48 49... 50--- 51name: test_sub_v8i16 52alignment: 4 53legalized: false 54regBankSelected: false 55registers: 56 - { id: 0, class: _ } 57 - { id: 1, class: _ } 58 - { id: 2, class: _ } 59body: | 60 bb.1 (%ir-block.0): 61 liveins: $xmm0, $xmm1 62 63 ; ALL-LABEL: name: test_sub_v8i16 64 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 65 ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF 66 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[DEF]], [[DEF1]] 67 ; ALL: RET 0 68 %0(<8 x s16>) = IMPLICIT_DEF 69 %1(<8 x s16>) = IMPLICIT_DEF 70 %2(<8 x s16>) = G_SUB %0, %1 71 $xmm0 = COPY %2 72 RET 0 73 74... 75--- 76name: test_sub_v4i32 77alignment: 4 78legalized: false 79regBankSelected: false 80registers: 81 - { id: 0, class: _ } 82 - { id: 1, class: _ } 83 - { id: 2, class: _ } 84body: | 85 bb.1 (%ir-block.0): 86 liveins: $xmm0, $xmm1 87 88 ; ALL-LABEL: name: test_sub_v4i32 89 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 90 ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF 91 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s32>) = G_SUB [[DEF]], [[DEF1]] 92 ; ALL: RET 0 93 %0(<4 x s32>) = IMPLICIT_DEF 94 %1(<4 x s32>) = IMPLICIT_DEF 95 %2(<4 x s32>) = G_SUB %0, %1 96 $xmm0 = COPY %2 97 RET 0 98 99... 100--- 101name: test_sub_v2i64 102alignment: 4 103legalized: false 104regBankSelected: false 105registers: 106 - { id: 0, class: _ } 107 - { id: 1, class: _ } 108 - { id: 2, class: _ } 109body: | 110 bb.1 (%ir-block.0): 111 liveins: $xmm0, $xmm1 112 113 ; ALL-LABEL: name: test_sub_v2i64 114 ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 115 ; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF 116 ; ALL: [[SUB:%[0-9]+]]:_(<2 x s64>) = G_SUB [[DEF]], [[DEF1]] 117 ; ALL: RET 0 118 %0(<2 x s64>) = IMPLICIT_DEF 119 %1(<2 x s64>) = IMPLICIT_DEF 120 %2(<2 x s64>) = G_SUB %0, %1 121 $xmm0 = COPY %2 122 RET 0 123 124... 125