1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2 3# TODO: add tests for additional configuration after the legalization supported 4--- | 5 define void @test_sub_v32i8() { 6 %ret = sub <32 x i8> undef, undef 7 ret void 8 } 9 10 define void @test_sub_v16i16() { 11 %ret = sub <16 x i16> undef, undef 12 ret void 13 } 14 15 define void @test_sub_v8i32() { 16 %ret = sub <8 x i32> undef, undef 17 ret void 18 } 19 20 define void @test_sub_v4i64() { 21 %ret = sub <4 x i64> undef, undef 22 ret void 23 } 24 25... 26--- 27name: test_sub_v32i8 28alignment: 4 29legalized: false 30regBankSelected: false 31registers: 32 - { id: 0, class: _ } 33 - { id: 1, class: _ } 34 - { id: 2, class: _ } 35body: | 36 bb.1 (%ir-block.0): 37 liveins: $ymm0, $ymm1 38 39 ; ALL-LABEL: name: test_sub_v32i8 40 ; ALL: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF 41 ; ALL: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF 42 ; ALL: [[SUB:%[0-9]+]]:_(<32 x s8>) = G_SUB [[DEF]], [[DEF1]] 43 ; ALL: RET 0 44 %0(<32 x s8>) = IMPLICIT_DEF 45 %1(<32 x s8>) = IMPLICIT_DEF 46 %2(<32 x s8>) = G_SUB %0, %1 47 $ymm0 = COPY %2 48 RET 0 49 50... 51--- 52name: test_sub_v16i16 53alignment: 4 54legalized: false 55regBankSelected: false 56registers: 57 - { id: 0, class: _ } 58 - { id: 1, class: _ } 59 - { id: 2, class: _ } 60body: | 61 bb.1 (%ir-block.0): 62 liveins: $ymm0, $ymm1 63 64 ; ALL-LABEL: name: test_sub_v16i16 65 ; ALL: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF 66 ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF 67 ; ALL: [[SUB:%[0-9]+]]:_(<16 x s16>) = G_SUB [[DEF]], [[DEF1]] 68 ; ALL: RET 0 69 %0(<16 x s16>) = IMPLICIT_DEF 70 %1(<16 x s16>) = IMPLICIT_DEF 71 %2(<16 x s16>) = G_SUB %0, %1 72 $ymm0 = COPY %2 73 RET 0 74 75... 76--- 77name: test_sub_v8i32 78alignment: 4 79legalized: false 80regBankSelected: false 81registers: 82 - { id: 0, class: _ } 83 - { id: 1, class: _ } 84 - { id: 2, class: _ } 85body: | 86 bb.1 (%ir-block.0): 87 liveins: $ymm0, $ymm1 88 89 ; ALL-LABEL: name: test_sub_v8i32 90 ; ALL: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF 91 ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF 92 ; ALL: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[DEF]], [[DEF1]] 93 ; ALL: RET 0 94 %0(<8 x s32>) = IMPLICIT_DEF 95 %1(<8 x s32>) = IMPLICIT_DEF 96 %2(<8 x s32>) = G_SUB %0, %1 97 $ymm0 = COPY %2 98 RET 0 99 100... 101--- 102name: test_sub_v4i64 103alignment: 4 104legalized: false 105regBankSelected: false 106registers: 107 - { id: 0, class: _ } 108 - { id: 1, class: _ } 109 - { id: 2, class: _ } 110body: | 111 bb.1 (%ir-block.0): 112 liveins: $ymm0, $ymm1 113 114 ; ALL-LABEL: name: test_sub_v4i64 115 ; ALL: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF 116 ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF 117 ; ALL: [[SUB:%[0-9]+]]:_(<4 x s64>) = G_SUB [[DEF]], [[DEF1]] 118 ; ALL: RET 0 119 %0(<4 x s64>) = IMPLICIT_DEF 120 %1(<4 x s64>) = IMPLICIT_DEF 121 %2(<4 x s64>) = G_SUB %0, %1 122 $ymm0 = COPY %2 123 RET 0 124 125... 126