1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 --global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY 3 4--- | 5 define void @test_mul_vec256() { 6 ret void 7 } 8 9 define void @test_add_vec256() { 10 ret void 11 } 12 13 define void @test_sub_vec256() { 14 ret void 15 } 16 17 define <8 x i32> @test_load_v8i32_noalign(<8 x i32>* %p1) { 18 %r = load <8 x i32>, <8 x i32>* %p1, align 1 19 ret <8 x i32> %r 20 } 21 22 define void @test_store_v8i32_noalign(<8 x i32> %val, <8 x i32>* %p1) { 23 store <8 x i32> %val, <8 x i32>* %p1, align 1 24 ret void 25 } 26 27--- 28name: test_mul_vec256 29alignment: 4 30legalized: true 31regBankSelected: false 32selected: false 33tracksRegLiveness: true 34# CHECK-LABEL: name: test_mul_vec256 35# CHECK: registers: 36# CHECK: - { id: 0, class: vecr, preferred-register: '' } 37# CHECK: - { id: 1, class: vecr, preferred-register: '' } 38registers: 39 - { id: 0, class: _ } 40 - { id: 1, class: _ } 41 - { id: 2, class: _ } 42body: | 43 bb.1 (%ir-block.0): 44 45 %0(<8 x s32>) = IMPLICIT_DEF 46 %1(<8 x s32>) = G_MUL %0, %0 47 RET 0 48 49... 50--- 51name: test_add_vec256 52alignment: 4 53legalized: true 54regBankSelected: false 55selected: false 56tracksRegLiveness: true 57# CHECK-LABEL: name: test_add_vec256 58# CHECK: registers: 59# CHECK: - { id: 0, class: vecr, preferred-register: '' } 60# CHECK: - { id: 1, class: vecr, preferred-register: '' } 61registers: 62 - { id: 0, class: _ } 63 - { id: 1, class: _ } 64 - { id: 2, class: _ } 65body: | 66 bb.1 (%ir-block.0): 67 68 %0(<8 x s32>) = IMPLICIT_DEF 69 %1(<8 x s32>) = G_ADD %0, %0 70 RET 0 71 72... 73--- 74name: test_sub_vec256 75alignment: 4 76legalized: true 77regBankSelected: false 78selected: false 79tracksRegLiveness: true 80# CHECK-LABEL: name: test_sub_vec256 81# CHECK: registers: 82# CHECK: - { id: 0, class: vecr, preferred-register: '' } 83# CHECK: - { id: 1, class: vecr, preferred-register: '' } 84registers: 85 - { id: 0, class: _ } 86 - { id: 1, class: _ } 87 - { id: 2, class: _ } 88body: | 89 bb.1 (%ir-block.0): 90 91 %0(<8 x s32>) = IMPLICIT_DEF 92 %1(<8 x s32>) = G_SUB %0, %0 93 RET 0 94 95... 96--- 97name: test_load_v8i32_noalign 98# CHECK-LABEL: name: test_load_v8i32_noalign 99alignment: 4 100legalized: true 101regBankSelected: false 102# CHECK: registers: 103# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } 104# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } 105registers: 106 - { id: 0, class: _ } 107 - { id: 1, class: _ } 108body: | 109 bb.1 (%ir-block.0): 110 liveins: $rdi 111 112 %0(p0) = COPY $rdi 113 %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1) 114 $ymm0 = COPY %1(<8 x s32>) 115 RET 0, implicit $ymm0 116 117... 118--- 119name: test_store_v8i32_noalign 120# CHECK-LABEL: name: test_store_v8i32_noalign 121alignment: 4 122legalized: true 123regBankSelected: false 124# CHECK: registers: 125# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } 126# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } 127registers: 128 - { id: 0, class: _ } 129 - { id: 1, class: _ } 130body: | 131 bb.1 (%ir-block.0): 132 liveins: $rdi, $ymm0 133 134 %0(<8 x s32>) = COPY $ymm0 135 %1(p0) = COPY $rdi 136 G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1) 137 RET 0 138 139... 140