1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY 3 4--- | 5 6 define void @test_mul_vec512() { 7 ret void 8 } 9 10 define void @test_add_vec512() { 11 ret void 12 } 13 14 define void @test_sub_vec512() { 15 ret void 16 } 17 18 define <16 x i32> @test_load_v16i32_noalign(<16 x i32>* %p1) { 19 %r = load <16 x i32>, <16 x i32>* %p1, align 1 20 ret <16 x i32> %r 21 } 22 23 define void @test_store_v16i32_noalign(<16 x i32> %val, <16 x i32>* %p1) { 24 store <16 x i32> %val, <16 x i32>* %p1, align 1 25 ret void 26 } 27 28... 29--- 30name: test_mul_vec512 31# CHECK-LABEL: name: test_mul_vec512 32alignment: 4 33legalized: true 34regBankSelected: false 35# CHECK: registers: 36# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } 37# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } 38registers: 39 - { id: 0, class: _ } 40 - { id: 1, class: _ } 41body: | 42 bb.1 (%ir-block.0): 43 44 %0(<16 x s32>) = IMPLICIT_DEF 45 %1(<16 x s32>) = G_MUL %0, %0 46 RET 0 47 48... 49--- 50name: test_add_vec512 51# CHECK-LABEL: name: test_add_vec512 52alignment: 4 53legalized: true 54regBankSelected: false 55# CHECK: registers: 56# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } 57# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } 58registers: 59 - { id: 0, class: _ } 60 - { id: 1, class: _ } 61body: | 62 bb.1 (%ir-block.0): 63 64 %0(<16 x s32>) = IMPLICIT_DEF 65 %1(<16 x s32>) = G_ADD %0, %0 66 RET 0 67 68... 69--- 70name: test_sub_vec512 71# CHECK-LABEL: name: test_sub_vec512 72alignment: 4 73legalized: true 74regBankSelected: false 75# CHECK: registers: 76# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } 77# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } 78registers: 79 - { id: 0, class: _ } 80 - { id: 1, class: _ } 81body: | 82 bb.1 (%ir-block.0): 83 84 %0(<16 x s32>) = IMPLICIT_DEF 85 %1(<16 x s32>) = G_SUB %0, %0 86 RET 0 87... 88--- 89 90name: test_load_v16i32_noalign 91# CHECK-LABEL: name: test_load_v16i32_noalign 92alignment: 4 93legalized: true 94regBankSelected: false 95# CHECK: registers: 96# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } 97# CHECK-NEXT: - { id: 1, class: vecr, preferred-register: '' } 98registers: 99 - { id: 0, class: _ } 100 - { id: 1, class: _ } 101body: | 102 bb.1 (%ir-block.0): 103 liveins: $rdi 104 105 %0(p0) = COPY $rdi 106 %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1) 107 $zmm0 = COPY %1(<16 x s32>) 108 RET 0, implicit $zmm0 109 110... 111--- 112name: test_store_v16i32_noalign 113# CHECK-LABEL: name: test_store_v16i32_noalign 114alignment: 4 115legalized: true 116regBankSelected: false 117# CHECK: registers: 118# CHECK-NEXT: - { id: 0, class: vecr, preferred-register: '' } 119# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } 120registers: 121 - { id: 0, class: _ } 122 - { id: 1, class: _ } 123body: | 124 bb.1 (%ir-block.0): 125 liveins: $rdi, $zmm0 126 127 %0(<16 x s32>) = COPY $zmm0 128 %1(p0) = COPY $rdi 129 G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1) 130 RET 0 131 132... 133