1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=SSE2 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NOVL --check-prefix=AVX1 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL 5 6--- | 7 define <16 x i8> @test_add_v16i8(<16 x i8> %arg1, <16 x i8> %arg2) { 8 %ret = add <16 x i8> %arg1, %arg2 9 ret <16 x i8> %ret 10 } 11 12 define <8 x i16> @test_add_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) { 13 %ret = add <8 x i16> %arg1, %arg2 14 ret <8 x i16> %ret 15 } 16 17 define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { 18 %ret = add <4 x i32> %arg1, %arg2 19 ret <4 x i32> %ret 20 } 21 22 define <2 x i64> @test_add_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) { 23 %ret = add <2 x i64> %arg1, %arg2 24 ret <2 x i64> %ret 25 } 26 27... 28--- 29name: test_add_v16i8 30# ALL-LABEL: name: test_add_v16i8 31alignment: 4 32legalized: true 33regBankSelected: true 34# NOVL: registers: 35# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 36# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 37# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 38# 39# AVX512VL: registers: 40# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 41# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 42# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 43# 44# AVX512BWVL: registers: 45# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 46# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 47# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 48registers: 49 - { id: 0, class: vecr } 50 - { id: 1, class: vecr } 51 - { id: 2, class: vecr } 52# SSE2: %2:vr128 = PADDBrr %0, %1 53# 54# AVX1: %2:vr128 = VPADDBrr %0, %1 55# 56# AVX512VL: %2:vr128 = VPADDBrr %0, %1 57# 58# AVX512BWVL: %2:vr128x = VPADDBZ128rr %0, %1 59body: | 60 bb.1 (%ir-block.0): 61 liveins: $xmm0, $xmm1 62 63 %0(<16 x s8>) = COPY $xmm0 64 %1(<16 x s8>) = COPY $xmm1 65 %2(<16 x s8>) = G_ADD %0, %1 66 $xmm0 = COPY %2(<16 x s8>) 67 RET 0, implicit $xmm0 68 69... 70--- 71name: test_add_v8i16 72# ALL-LABEL: name: test_add_v8i16 73alignment: 4 74legalized: true 75regBankSelected: true 76# NOVL: registers: 77# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 78# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 79# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 80# 81# AVX512VL: registers: 82# AVX512VL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 83# AVX512VL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 84# AVX512VL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 85# 86# AVX512BWVL: registers: 87# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 88# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 89# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 90registers: 91 - { id: 0, class: vecr } 92 - { id: 1, class: vecr } 93 - { id: 2, class: vecr } 94# SSE2: %2:vr128 = PADDWrr %0, %1 95# 96# AVX1: %2:vr128 = VPADDWrr %0, %1 97# 98# AVX512VL: %2:vr128 = VPADDWrr %0, %1 99# 100# AVX512BWVL: %2:vr128x = VPADDWZ128rr %0, %1 101body: | 102 bb.1 (%ir-block.0): 103 liveins: $xmm0, $xmm1 104 105 %0(<8 x s16>) = COPY $xmm0 106 %1(<8 x s16>) = COPY $xmm1 107 %2(<8 x s16>) = G_ADD %0, %1 108 $xmm0 = COPY %2(<8 x s16>) 109 RET 0, implicit $xmm0 110 111... 112--- 113name: test_add_v4i32 114# ALL-LABEL: name: test_add_v4i32 115alignment: 4 116legalized: true 117regBankSelected: true 118# NOVL: registers: 119# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 120# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 121# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 122# 123# AVX512VL: registers: 124# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 125# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 126# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 127# 128# AVX512BWVL: registers: 129# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 130# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 131# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 132registers: 133 - { id: 0, class: vecr } 134 - { id: 1, class: vecr } 135 - { id: 2, class: vecr } 136# SSE2: %2:vr128 = PADDDrr %0, %1 137# 138# AVX1: %2:vr128 = VPADDDrr %0, %1 139# 140# AVX512VL: %2:vr128x = VPADDDZ128rr %0, %1 141# 142# AVX512BWVL: %2:vr128x = VPADDDZ128rr %0, %1 143body: | 144 bb.1 (%ir-block.0): 145 liveins: $xmm0, $xmm1 146 147 %0(<4 x s32>) = COPY $xmm0 148 %1(<4 x s32>) = COPY $xmm1 149 %2(<4 x s32>) = G_ADD %0, %1 150 $xmm0 = COPY %2(<4 x s32>) 151 RET 0, implicit $xmm0 152 153... 154--- 155name: test_add_v2i64 156# ALL-LABEL: name: test_add_v2i64 157alignment: 4 158legalized: true 159regBankSelected: true 160# NOVL: registers: 161# NOVL-NEXT: - { id: 0, class: vr128, preferred-register: '' } 162# NOVL-NEXT: - { id: 1, class: vr128, preferred-register: '' } 163# NOVL-NEXT: - { id: 2, class: vr128, preferred-register: '' } 164# 165# AVX512VL: registers: 166# AVX512VL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 167# AVX512VL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 168# AVX512VL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 169# 170# AVX512BWVL: registers: 171# AVX512BWVL-NEXT: - { id: 0, class: vr128x, preferred-register: '' } 172# AVX512BWVL-NEXT: - { id: 1, class: vr128x, preferred-register: '' } 173# AVX512BWVL-NEXT: - { id: 2, class: vr128x, preferred-register: '' } 174registers: 175 - { id: 0, class: vecr } 176 - { id: 1, class: vecr } 177 - { id: 2, class: vecr } 178# SSE2: %2:vr128 = PADDQrr %0, %1 179# 180# AVX1: %2:vr128 = VPADDQrr %0, %1 181# 182# AVX512VL: %2:vr128x = VPADDQZ128rr %0, %1 183# 184# AVX512BWVL: %2:vr128x = VPADDQZ128rr %0, %1 185body: | 186 bb.1 (%ir-block.0): 187 liveins: $xmm0, $xmm1 188 189 %0(<2 x s64>) = COPY $xmm0 190 %1(<2 x s64>) = COPY $xmm1 191 %2(<2 x s64>) = G_ADD %0, %1 192 $xmm0 = COPY %2(<2 x s64>) 193 RET 0, implicit $xmm0 194 195... 196