1# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL 4 5--- | 6 define <32 x i8> @test_add_v32i8(<32 x i8> %arg1, <32 x i8> %arg2) { 7 %ret = add <32 x i8> %arg1, %arg2 8 ret <32 x i8> %ret 9 } 10 11 define <16 x i16> @test_add_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) { 12 %ret = add <16 x i16> %arg1, %arg2 13 ret <16 x i16> %ret 14 } 15 16 define <8 x i32> @test_add_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) { 17 %ret = add <8 x i32> %arg1, %arg2 18 ret <8 x i32> %ret 19 } 20 21 define <4 x i64> @test_add_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) { 22 %ret = add <4 x i64> %arg1, %arg2 23 ret <4 x i64> %ret 24 } 25... 26--- 27name: test_add_v32i8 28# ALL-LABEL: name: test_add_v32i8 29alignment: 4 30legalized: true 31regBankSelected: true 32# AVX2: registers: 33# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } 34# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } 35# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } 36# 37# AVX512VL: registers: 38# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } 39# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } 40# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } 41# 42# AVX512BWVL: registers: 43# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 44# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 45# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 46registers: 47 - { id: 0, class: vecr } 48 - { id: 1, class: vecr } 49 - { id: 2, class: vecr } 50# AVX2: %2:vr256 = VPADDBYrr %0, %1 51# 52# AVX512VL: %2:vr256 = VPADDBYrr %0, %1 53# 54# AVX512BWVL: %2:vr256x = VPADDBZ256rr %0, %1 55body: | 56 bb.1 (%ir-block.0): 57 liveins: $ymm0, $ymm1 58 59 %0(<32 x s8>) = COPY $ymm0 60 %1(<32 x s8>) = COPY $ymm1 61 %2(<32 x s8>) = G_ADD %0, %1 62 $ymm0 = COPY %2(<32 x s8>) 63 RET 0, implicit $ymm0 64 65... 66--- 67name: test_add_v16i16 68# ALL-LABEL: name: test_add_v16i16 69alignment: 4 70legalized: true 71regBankSelected: true 72# AVX2: registers: 73# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } 74# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } 75# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } 76# 77# AVX512VL: registers: 78# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' } 79# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' } 80# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' } 81# 82# AVX512BWVL: registers: 83# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 84# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 85# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 86registers: 87 - { id: 0, class: vecr } 88 - { id: 1, class: vecr } 89 - { id: 2, class: vecr } 90# AVX2: %2:vr256 = VPADDWYrr %0, %1 91# 92# AVX512VL: %2:vr256 = VPADDWYrr %0, %1 93# 94# AVX512BWVL: %2:vr256x = VPADDWZ256rr %0, %1 95body: | 96 bb.1 (%ir-block.0): 97 liveins: $ymm0, $ymm1 98 99 %0(<16 x s16>) = COPY $ymm0 100 %1(<16 x s16>) = COPY $ymm1 101 %2(<16 x s16>) = G_ADD %0, %1 102 $ymm0 = COPY %2(<16 x s16>) 103 RET 0, implicit $ymm0 104 105... 106--- 107name: test_add_v8i32 108# ALL-LABEL: name: test_add_v8i32 109alignment: 4 110legalized: true 111regBankSelected: true 112# AVX2: registers: 113# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } 114# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } 115# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } 116# 117# AVX512VL: registers: 118# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 119# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 120# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 121# 122# AVX512BWVL: registers: 123# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 124# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 125# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 126registers: 127 - { id: 0, class: vecr } 128 - { id: 1, class: vecr } 129 - { id: 2, class: vecr } 130# AVX2: %2:vr256 = VPADDDYrr %0, %1 131# 132# AVX512VL: %2:vr256x = VPADDDZ256rr %0, %1 133# 134# AVX512BWVL: %2:vr256x = VPADDDZ256rr %0, %1 135body: | 136 bb.1 (%ir-block.0): 137 liveins: $ymm0, $ymm1 138 139 %0(<8 x s32>) = COPY $ymm0 140 %1(<8 x s32>) = COPY $ymm1 141 %2(<8 x s32>) = G_ADD %0, %1 142 $ymm0 = COPY %2(<8 x s32>) 143 RET 0, implicit $ymm0 144 145... 146--- 147name: test_add_v4i64 148# ALL-LABEL: name: test_add_v4i64 149alignment: 4 150legalized: true 151regBankSelected: true 152# AVX2: registers: 153# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' } 154# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' } 155# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' } 156# 157# AVX512VL: registers: 158# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 159# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 160# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 161# 162# AVX512BWVL: registers: 163# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' } 164# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' } 165# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' } 166registers: 167 - { id: 0, class: vecr } 168 - { id: 1, class: vecr } 169 - { id: 2, class: vecr } 170# AVX2: %2:vr256 = VPADDQYrr %0, %1 171# 172# AVX512VL: %2:vr256x = VPADDQZ256rr %0, %1 173# 174# AVX512BWVL: %2:vr256x = VPADDQZ256rr %0, %1 175body: | 176 bb.1 (%ir-block.0): 177 liveins: $ymm0, $ymm1 178 179 %0(<4 x s64>) = COPY $ymm0 180 %1(<4 x s64>) = COPY $ymm1 181 %2(<4 x s64>) = G_ADD %0, %1 182 $ymm0 = COPY %2(<4 x s64>) 183 RET 0, implicit $ymm0 184 185... 186