1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL 5 6--- | 7 define i64 @test_add_i64(i64 %arg1, i64 %arg2) { 8 %ret = add i64 %arg1, %arg2 9 ret i64 %ret 10 } 11 12 define i32 @test_add_i32(i32 %arg1, i32 %arg2) { 13 %ret = add i32 %arg1, %arg2 14 ret i32 %ret 15 } 16 17 define i16 @test_add_i16(i16 %arg1, i16 %arg2) { 18 %ret = add i16 %arg1, %arg2 19 ret i16 %ret 20 } 21 22 define i8 @test_add_i8(i8 %arg1, i8 %arg2) { 23 %ret = add i8 %arg1, %arg2 24 ret i8 %ret 25 } 26 27 define <4 x i32> @test_add_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { 28 %ret = add <4 x i32> %arg1, %arg2 29 ret <4 x i32> %ret 30 } 31 32 define <4 x float> @test_add_v4f32(<4 x float> %arg1, <4 x float> %arg2) { 33 %ret = fadd <4 x float> %arg1, %arg2 34 ret <4 x float> %ret 35 } 36... 37 38--- 39name: test_add_i64 40# ALL-LABEL: name: test_add_i64 41legalized: true 42regBankSelected: true 43registers: 44 - { id: 0, class: gpr } 45 - { id: 1, class: gpr } 46 - { id: 2, class: gpr } 47# ALL: %0:gr64 = COPY $rdi 48# ALL-NEXT: %1:gr64 = COPY $rsi 49# ALL-NEXT: %2:gr64 = ADD64rr %0, %1 50body: | 51 bb.1 (%ir-block.0): 52 liveins: $edi, $esi 53 54 %0(s64) = COPY $rdi 55 %1(s64) = COPY $rsi 56 %2(s64) = G_ADD %0, %1 57 $rax = COPY %2(s64) 58 59... 60 61--- 62name: test_add_i32 63# ALL-LABEL: name: test_add_i32 64legalized: true 65regBankSelected: true 66registers: 67 - { id: 0, class: gpr } 68 - { id: 1, class: gpr } 69 - { id: 2, class: gpr } 70# ALL: %0:gr32 = COPY $edi 71# ALL-NEXT: %1:gr32 = COPY $esi 72# ALL-NEXT: %2:gr32 = ADD32rr %0, %1 73body: | 74 bb.1 (%ir-block.0): 75 liveins: $edi, $esi 76 77 %0(s32) = COPY $edi 78 %1(s32) = COPY $esi 79 %2(s32) = G_ADD %0, %1 80 $eax = COPY %2(s32) 81 82... 83--- 84name: test_add_i16 85# ALL-LABEL: name: test_add_i16 86alignment: 4 87legalized: true 88regBankSelected: true 89selected: false 90registers: 91 - { id: 0, class: gpr } 92 - { id: 1, class: gpr } 93 - { id: 2, class: gpr } 94# ALL: %0:gr16 = COPY $di 95# ALL: %1:gr16 = COPY $si 96# ALL: %2:gr16 = ADD16rr %0, %1, implicit-def $eflags 97body: | 98 bb.1 (%ir-block.0): 99 liveins: $edi, $esi 100 101 %0(s16) = COPY $di 102 %1(s16) = COPY $si 103 %2(s16) = G_ADD %0, %1 104 $ax = COPY %2(s16) 105 RET 0, implicit $ax 106 107... 108--- 109name: test_add_i8 110# ALL-LABEL: name: test_add_i8 111alignment: 4 112legalized: true 113regBankSelected: true 114selected: false 115registers: 116 - { id: 0, class: gpr } 117 - { id: 1, class: gpr } 118 - { id: 2, class: gpr } 119# ALL: %0:gr8 = COPY $dil 120# ALL: %1:gr8 = COPY $sil 121# ALL: %2:gr8 = ADD8rr %0, %1, implicit-def $eflags 122body: | 123 bb.1 (%ir-block.0): 124 liveins: $edi, $esi 125 126 %0(s8) = COPY $dil 127 %1(s8) = COPY $sil 128 %2(s8) = G_ADD %0, %1 129 $al = COPY %2(s8) 130 RET 0, implicit $al 131 132... 133--- 134name: test_add_v4i32 135# ALL-LABEL: name: test_add_v4i32 136alignment: 4 137legalized: true 138regBankSelected: true 139selected: false 140tracksRegLiveness: true 141registers: 142 - { id: 0, class: vecr } 143 - { id: 1, class: vecr } 144 - { id: 2, class: vecr } 145# NO_AVX512VL: %0:vr128 = COPY $xmm0 146# NO_AVX512VL: %1:vr128 = COPY $xmm1 147# SSE-NEXT: %2:vr128 = PADDDrr %0, %1 148# AVX-NEXT: %2:vr128 = VPADDDrr %0, %1 149# AVX512F-NEXT: %2:vr128 = VPADDDrr %0, %1 150# AVX512VL: %0:vr128x = COPY $xmm0 151# AVX512VL: %1:vr128x = COPY $xmm1 152# AVX512VL-NEXT: %2:vr128x = VPADDDZ128rr %0, %1 153body: | 154 bb.1 (%ir-block.0): 155 liveins: $xmm0, $xmm1 156 157 %0(<4 x s32>) = COPY $xmm0 158 %1(<4 x s32>) = COPY $xmm1 159 %2(<4 x s32>) = G_ADD %0, %1 160 $xmm0 = COPY %2(<4 x s32>) 161 RET 0, implicit $xmm0 162 163... 164--- 165name: test_add_v4f32 166# ALL-LABEL: name: test_add_v4f32 167alignment: 4 168legalized: true 169regBankSelected: true 170selected: false 171tracksRegLiveness: true 172registers: 173 - { id: 0, class: vecr } 174 - { id: 1, class: vecr } 175 - { id: 2, class: vecr } 176# SSE: %0:vr128 = COPY $xmm0 177# SSE-NEXT: %1:vr128 = COPY $xmm1 178# SSE-NEXT: %2:vr128 = ADDPSrr %0, %1 179# AVX: %0:vr128 = COPY $xmm0 180# AVX-NEXT: %1:vr128 = COPY $xmm1 181# AVX-NEXT: %2:vr128 = VADDPSrr %0, %1 182# AVX512F: %0:vr128 = COPY $xmm0 183# AVX512F-NEXT: 1:vr128 = COPY $xmm1 184# AVX512F-NEXT: %2:vr128 = VADDPSrr %0, %1 185# AVX512VL: %0:vr128x = COPY $xmm0 186# AVX512VL-NEXT: %1:vr128x = COPY $xmm1 187# AVX512VL-NEXT: %2:vr128x = VADDPSZ128rr %0, %1 188body: | 189 bb.1 (%ir-block.0): 190 liveins: $xmm0, $xmm1 191 192 %0(<4 x s32>) = COPY $xmm0 193 %1(<4 x s32>) = COPY $xmm1 194 %2(<4 x s32>) = G_FADD %0, %1 195 $xmm0 = COPY %2(<4 x s32>) 196 RET 0, implicit $xmm0 197 198... 199