1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64 3 4--- | 5 define i64 @test_zext_i1(i8 %a) { 6 %val = trunc i8 %a to i1 7 %r = zext i1 %val to i64 8 ret i64 %r 9 } 10 11 define i64 @test_sext_i8(i8 %val) { 12 %r = sext i8 %val to i64 13 ret i64 %r 14 } 15 16 define i64 @test_sext_i16(i16 %val) { 17 %r = sext i16 %val to i64 18 ret i64 %r 19 } 20 21 define void @anyext_s64_from_s1() { ret void } 22 define void @anyext_s64_from_s8() { ret void } 23 define void @anyext_s64_from_s16() { ret void } 24 define void @anyext_s64_from_s32() { ret void } 25... 26--- 27name: test_zext_i1 28alignment: 4 29legalized: true 30regBankSelected: true 31registers: 32 - { id: 0, class: gpr } 33 - { id: 1, class: gpr } 34 - { id: 2, class: gpr } 35body: | 36 bb.1 (%ir-block.0): 37 liveins: $edi 38 39 ; ALL-LABEL: name: test_zext_i1 40 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil 41 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit 42 ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def $eflags 43 ; ALL: $rax = COPY [[AND64ri8_]] 44 ; ALL: RET 0, implicit $rax 45 %0(s8) = COPY $dil 46 %1(s1) = G_TRUNC %0(s8) 47 %2(s64) = G_ZEXT %1(s1) 48 $rax = COPY %2(s64) 49 RET 0, implicit $rax 50 51... 52--- 53name: test_sext_i8 54alignment: 4 55legalized: true 56regBankSelected: true 57registers: 58 - { id: 0, class: gpr } 59 - { id: 1, class: gpr } 60body: | 61 bb.1 (%ir-block.0): 62 liveins: $edi 63 64 ; ALL-LABEL: name: test_sext_i8 65 ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY $dil 66 ; ALL: [[MOVSX64rr8_:%[0-9]+]]:gr64 = MOVSX64rr8 [[COPY]] 67 ; ALL: $rax = COPY [[MOVSX64rr8_]] 68 ; ALL: RET 0, implicit $rax 69 %0(s8) = COPY $dil 70 %1(s64) = G_SEXT %0(s8) 71 $rax = COPY %1(s64) 72 RET 0, implicit $rax 73 74... 75--- 76name: test_sext_i16 77alignment: 4 78legalized: true 79regBankSelected: true 80registers: 81 - { id: 0, class: gpr } 82 - { id: 1, class: gpr } 83body: | 84 bb.1 (%ir-block.0): 85 liveins: $edi 86 87 ; ALL-LABEL: name: test_sext_i16 88 ; ALL: [[COPY:%[0-9]+]]:gr16 = COPY $di 89 ; ALL: [[MOVSX64rr16_:%[0-9]+]]:gr64 = MOVSX64rr16 [[COPY]] 90 ; ALL: $rax = COPY [[MOVSX64rr16_]] 91 ; ALL: RET 0, implicit $rax 92 %0(s16) = COPY $di 93 %1(s64) = G_SEXT %0(s16) 94 $rax = COPY %1(s64) 95 RET 0, implicit $rax 96 97... 98--- 99name: anyext_s64_from_s1 100alignment: 4 101legalized: true 102regBankSelected: true 103registers: 104 - { id: 0, class: gpr } 105 - { id: 1, class: gpr } 106 - { id: 2, class: gpr } 107body: | 108 bb.1 (%ir-block.0): 109 liveins: $edi 110 111 ; ALL-LABEL: name: anyext_s64_from_s1 112 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi 113 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 114 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit 115 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 116 ; ALL: RET 0, implicit $rax 117 %0(s64) = COPY $rdi 118 %1(s1) = G_TRUNC %0(s64) 119 %2(s64) = G_ANYEXT %1(s1) 120 $rax = COPY %2(s64) 121 RET 0, implicit $rax 122... 123--- 124name: anyext_s64_from_s8 125alignment: 4 126legalized: true 127regBankSelected: true 128registers: 129 - { id: 0, class: gpr } 130 - { id: 1, class: gpr } 131 - { id: 2, class: gpr } 132body: | 133 bb.1 (%ir-block.0): 134 liveins: $edi 135 136 ; ALL-LABEL: name: anyext_s64_from_s8 137 ; ALL: [[COPY:%[0-9]+]]:gr64_with_sub_8bit = COPY $rdi 138 ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit 139 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit 140 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 141 ; ALL: RET 0, implicit $rax 142 %0(s64) = COPY $rdi 143 %1(s8) = G_TRUNC %0(s64) 144 %2(s64) = G_ANYEXT %1(s8) 145 $rax = COPY %2(s64) 146 RET 0, implicit $rax 147... 148--- 149name: anyext_s64_from_s16 150alignment: 4 151legalized: true 152regBankSelected: true 153registers: 154 - { id: 0, class: gpr } 155 - { id: 1, class: gpr } 156 - { id: 2, class: gpr } 157body: | 158 bb.1 (%ir-block.0): 159 liveins: $edi 160 161 ; ALL-LABEL: name: anyext_s64_from_s16 162 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 163 ; ALL: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit 164 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_16bit 165 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 166 ; ALL: RET 0, implicit $rax 167 %0(s64) = COPY $rdi 168 %1(s16) = G_TRUNC %0(s64) 169 %2(s64) = G_ANYEXT %1(s16) 170 $rax = COPY %2(s64) 171 RET 0, implicit $rax 172... 173--- 174name: anyext_s64_from_s32 175alignment: 4 176legalized: true 177regBankSelected: true 178registers: 179 - { id: 0, class: gpr } 180 - { id: 1, class: gpr } 181 - { id: 2, class: gpr } 182body: | 183 bb.1 (%ir-block.0): 184 liveins: $edi 185 186 ; ALL-LABEL: name: anyext_s64_from_s32 187 ; ALL: [[COPY:%[0-9]+]]:gr64 = COPY $rdi 188 ; ALL: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]].sub_32bit 189 ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32bit 190 ; ALL: $rax = COPY [[SUBREG_TO_REG]] 191 ; ALL: RET 0, implicit $rax 192 %0(s64) = COPY $rdi 193 %1(s32) = G_TRUNC %0(s64) 194 %2(s64) = G_ANYEXT %1(s32) 195 $rax = COPY %2(s64) 196 RET 0, implicit $rax 197... 198