1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL 5 6--- | 7 define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) { 8 %r = load <4 x i32>, <4 x i32>* %p1, align 1 9 ret <4 x i32> %r 10 } 11 12 define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) { 13 %r = load <4 x i32>, <4 x i32>* %p1, align 16 14 ret <4 x i32> %r 15 } 16 17 define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) { 18 store <4 x i32> %val, <4 x i32>* %p1, align 16 19 ret <4 x i32>* %p1 20 } 21 22 define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) { 23 store <4 x i32> %val, <4 x i32>* %p1, align 1 24 ret <4 x i32>* %p1 25 } 26 27... 28--- 29# ALL-LABEL: name: test_load_v4i32_noalign 30name: test_load_v4i32_noalign 31alignment: 4 32legalized: true 33regBankSelected: true 34registers: 35 - { id: 0, class: gpr } 36 - { id: 1, class: vecr } 37# ALL: %0:gr64 = COPY $rdi 38# SSE: %1:vr128 = MOVUPSrm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1, align 1) 39# AVX: %1:vr128 = VMOVUPSrm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1, align 1) 40# AVX512F: %1:vr128x = VMOVUPSZ128rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1, align 1) 41# AVX512VL: %1:vr128x = VMOVUPSZ128rm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1, align 1) 42# ALL: $xmm0 = COPY %1 43body: | 44 bb.1 (%ir-block.0): 45 liveins: $rdi 46 47 %0(p0) = COPY $rdi 48 %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1) 49 $xmm0 = COPY %1(<4 x s32>) 50 RET 0, implicit $xmm0 51 52... 53--- 54# ALL-LABEL: name: test_load_v4i32_align 55name: test_load_v4i32_align 56alignment: 4 57legalized: true 58regBankSelected: true 59registers: 60 - { id: 0, class: gpr } 61 - { id: 1, class: vecr } 62# ALL: %0:gr64 = COPY $rdi 63# SSE: %1:vr128 = MOVAPSrm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1) 64# AVX: %1:vr128 = VMOVAPSrm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1) 65# AVX512F: %1:vr128x = VMOVAPSZ128rm_NOVLX %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1) 66# AVX512VL: %1:vr128x = VMOVAPSZ128rm %0, 1, $noreg, 0, $noreg :: (load 16 from %ir.p1) 67# ALL: $xmm0 = COPY %1 68body: | 69 bb.1 (%ir-block.0): 70 liveins: $rdi 71 72 %0(p0) = COPY $rdi 73 %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1) 74 $xmm0 = COPY %1(<4 x s32>) 75 RET 0, implicit $xmm0 76 77... 78--- 79# ALL-LABEL: name: test_store_v4i32_align 80name: test_store_v4i32_align 81alignment: 4 82legalized: true 83regBankSelected: true 84registers: 85 - { id: 0, class: vecr } 86 - { id: 1, class: gpr } 87# NO_AVX512F: %0:vr128 = COPY $xmm0 88# AVX512ALL: %0:vr128x = COPY $xmm0 89# ALL: %1:gr64 = COPY $rdi 90# SSE: MOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1) 91# AVX: VMOVAPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1) 92# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1) 93# AVX512VL: VMOVAPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1) 94# ALL: $rax = COPY %1 95body: | 96 bb.1 (%ir-block.0): 97 liveins: $rdi, $xmm0 98 99 %0(<4 x s32>) = COPY $xmm0 100 %1(p0) = COPY $rdi 101 G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16) 102 $rax = COPY %1(p0) 103 RET 0, implicit $rax 104 105... 106--- 107# ALL-LABEL: name: test_store_v4i32_noalign 108name: test_store_v4i32_noalign 109alignment: 4 110legalized: true 111regBankSelected: true 112registers: 113 - { id: 0, class: vecr } 114 - { id: 1, class: gpr } 115# NO_AVX512F: %0:vr128 = COPY $xmm0 116# AVX512ALL: %0:vr128x = COPY $xmm0 117# ALL: %1:gr64 = COPY $rdi 118# SSE: MOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1, align 1) 119# AVX: VMOVUPSmr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1, align 1) 120# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1, align 1) 121# AVX512VL: VMOVUPSZ128mr %1, 1, $noreg, 0, $noreg, %0 :: (store 16 into %ir.p1, align 1) 122# ALL: $rax = COPY %1 123body: | 124 bb.1 (%ir-block.0): 125 liveins: $rdi, $xmm0 126 127 %0(<4 x s32>) = COPY $xmm0 128 %1(p0) = COPY $rdi 129 G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1) 130 $rax = COPY %1(p0) 131 RET 0, implicit $rax 132 133... 134