1# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE 2# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX 3# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F 4# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL 5 6--- | 7 define i64 @test_sub_i64(i64 %arg1, i64 %arg2) { 8 %ret = sub i64 %arg1, %arg2 9 ret i64 %ret 10 } 11 12 define i32 @test_sub_i32(i32 %arg1, i32 %arg2) { 13 %ret = sub i32 %arg1, %arg2 14 ret i32 %ret 15 } 16 17 define <4 x i32> @test_sub_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) { 18 %ret = sub <4 x i32> %arg1, %arg2 19 ret <4 x i32> %ret 20 } 21 22 define <4 x float> @test_sub_v4f32(<4 x float> %arg1, <4 x float> %arg2) { 23 %ret = fsub <4 x float> %arg1, %arg2 24 ret <4 x float> %ret 25 } 26 27... 28--- 29name: test_sub_i64 30legalized: true 31regBankSelected: true 32registers: 33 - { id: 0, class: gpr } 34 - { id: 1, class: gpr } 35 - { id: 2, class: gpr } 36# ALL: %0:gr64 = COPY $rdi 37# ALL-NEXT: %1:gr64 = COPY $rsi 38# ALL-NEXT: %2:gr64 = SUB64rr %0, %1 39body: | 40 bb.1 (%ir-block.0): 41 liveins: $edi, $esi 42 43 %0(s64) = COPY $rdi 44 %1(s64) = COPY $rsi 45 %2(s64) = G_SUB %0, %1 46 $rax = COPY %2(s64) 47 48... 49 50--- 51name: test_sub_i32 52legalized: true 53regBankSelected: true 54registers: 55 - { id: 0, class: gpr } 56 - { id: 1, class: gpr } 57 - { id: 2, class: gpr } 58# ALL: %0:gr32 = COPY $edi 59# ALL-NEXT: %1:gr32 = COPY $esi 60# ALL-NEXT: %2:gr32 = SUB32rr %0, %1 61body: | 62 bb.1 (%ir-block.0): 63 liveins: $edi, $esi 64 65 %0(s32) = COPY $edi 66 %1(s32) = COPY $esi 67 %2(s32) = G_SUB %0, %1 68 $eax = COPY %2(s32) 69 70... 71--- 72name: test_sub_v4i32 73alignment: 4 74legalized: true 75regBankSelected: true 76selected: false 77tracksRegLiveness: true 78registers: 79 - { id: 0, class: vecr } 80 - { id: 1, class: vecr } 81 - { id: 2, class: vecr } 82# NO_AVX512VL: %0:vr128 = COPY $xmm0 83# AVX512VL: %0:vr128x = COPY $xmm0 84# NO_AVX512VL: %1:vr128 = COPY $xmm1 85# AVX512VL: %1:vr128x = COPY $xmm1 86# SSE-NEXT: %2:vr128 = PSUBDrr %0, %1 87# AVX-NEXT: %2:vr128 = VPSUBDrr %0, %1 88# AVX512F-NEXT: %2:vr128 = VPSUBDrr %0, %1 89# AVX512VL-NEXT: %2:vr128x = VPSUBDZ128rr %0, %1 90body: | 91 bb.1 (%ir-block.0): 92 liveins: $xmm0, $xmm1 93 94 %0(<4 x s32>) = COPY $xmm0 95 %1(<4 x s32>) = COPY $xmm1 96 %2(<4 x s32>) = G_SUB %0, %1 97 $xmm0 = COPY %2(<4 x s32>) 98 RET 0, implicit $xmm0 99 100... 101--- 102name: test_sub_v4f32 103alignment: 4 104legalized: true 105regBankSelected: true 106selected: false 107tracksRegLiveness: true 108registers: 109 - { id: 0, class: vecr } 110 - { id: 1, class: vecr } 111 - { id: 2, class: vecr } 112# NO_AVX512VL: %0:vr128 = COPY $xmm0 113# NO_AVX512VL: %1:vr128 = COPY $xmm1 114# SSE-NEXT: %2:vr128 = SUBPSrr %0, %1 115# AVX-NEXT: %2:vr128 = VSUBPSrr %0, %1 116# AVX512F-NEXT: %2:vr128 = VSUBPSrr %0, %1 117# 118# AVX512VL: %0:vr128x = COPY $xmm0 119# AVX512VL: %1:vr128x = COPY $xmm1 120# AVX512VL-NEXT: %2:vr128x = VSUBPSZ128rr %0, %1 121body: | 122 bb.1 (%ir-block.0): 123 liveins: $xmm0, $xmm1 124 125 %0(<4 x s32>) = COPY $xmm0 126 %1(<4 x s32>) = COPY $xmm1 127 %2(<4 x s32>) = G_FSUB %0, %1 128 $xmm0 = COPY %2(<4 x s32>) 129 RET 0, implicit $xmm0 130 131... 132