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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=CHECK --check-prefix=AVX2
3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s  --check-prefix=CHECK  --check-prefix=AVX512  --check-prefix=AVX512F
4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s  --check-prefix=CHECK  --check-prefix=AVX512  --check-prefix=AVX512VL
5
6; fold (abs c1) -> c2
7define <4 x i32> @combine_v4i32_abs_constant() {
8; CHECK-LABEL: combine_v4i32_abs_constant:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vmovaps {{.*#+}} xmm0 = [0,1,3,2147483648]
11; CHECK-NEXT:    retq
12  %1 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> <i32 0, i32 -1, i32 3, i32 -2147483648>)
13  ret <4 x i32> %1
14}
15
16define <16 x i16> @combine_v16i16_abs_constant() {
17; CHECK-LABEL: combine_v16i16_abs_constant:
18; CHECK:       # %bb.0:
19; CHECK-NEXT:    vmovaps {{.*#+}} ymm0 = [0,1,1,3,3,7,7,255,255,4096,4096,32767,32767,32768,32768,0]
20; CHECK-NEXT:    retq
21  %1 = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> <i16 0, i16 1, i16 -1, i16 3, i16 -3, i16 7, i16 -7, i16 255, i16 -255, i16 4096, i16 -4096, i16 32767, i16 -32767, i16 -32768, i16 32768, i16 65536>)
22  ret <16 x i16> %1
23}
24
25; fold (abs (abs x)) -> (abs x)
26define i32 @combine_i32_abs_abs(i32 %a) {
27; CHECK-LABEL: combine_i32_abs_abs:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    movl %edi, %eax
30; CHECK-NEXT:    negl %eax
31; CHECK-NEXT:    cmovll %edi, %eax
32; CHECK-NEXT:    retq
33  %n1 = sub i32 zeroinitializer, %a
34  %b1 = icmp slt i32 %a, zeroinitializer
35  %a1 = select i1 %b1, i32 %n1, i32 %a
36  %n2 = sub i32 zeroinitializer, %a1
37  %b2 = icmp sgt i32 %a1, zeroinitializer
38  %a2 = select i1 %b2, i32 %a1, i32 %n2
39  ret i32 %a2
40}
41
42define <8 x i16> @combine_v8i16_abs_abs(<8 x i16> %a) {
43; CHECK-LABEL: combine_v8i16_abs_abs:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    vpabsw %xmm0, %xmm0
46; CHECK-NEXT:    retq
47  %a1 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a)
48  %s2 = ashr <8 x i16> %a1, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
49  %a2 = add <8 x i16> %a1, %s2
50  %x2 = xor <8 x i16> %a2, %s2
51  ret <8 x i16> %x2
52}
53
54define <32 x i8> @combine_v32i8_abs_abs(<32 x i8> %a) {
55; CHECK-LABEL: combine_v32i8_abs_abs:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    vpabsb %ymm0, %ymm0
58; CHECK-NEXT:    retq
59  %n1 = sub <32 x i8> zeroinitializer, %a
60  %b1 = icmp slt <32 x i8> %a, zeroinitializer
61  %a1 = select <32 x i1> %b1, <32 x i8> %n1, <32 x i8> %a
62  %a2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a1)
63  ret <32 x i8> %a2
64}
65
66define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) {
67; AVX2-LABEL: combine_v4i64_abs_abs:
68; AVX2:       # %bb.0:
69; AVX2-NEXT:    vpxor %xmm1, %xmm1, %xmm1
70; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm2
71; AVX2-NEXT:    vpaddq %ymm2, %ymm0, %ymm0
72; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm0
73; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm1, %ymm1
74; AVX2-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
75; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
76; AVX2-NEXT:    retq
77;
78; AVX512F-LABEL: combine_v4i64_abs_abs:
79; AVX512F:       # %bb.0:
80; AVX512F-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
81; AVX512F-NEXT:    vpabsq %zmm0, %zmm0
82; AVX512F-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
83; AVX512F-NEXT:    retq
84;
85; AVX512VL-LABEL: combine_v4i64_abs_abs:
86; AVX512VL:       # %bb.0:
87; AVX512VL-NEXT:    vpabsq %ymm0, %ymm0
88; AVX512VL-NEXT:    retq
89  %n1 = sub <4 x i64> zeroinitializer, %a
90  %b1 = icmp slt <4 x i64> %a, zeroinitializer
91  %a1 = select <4 x i1> %b1, <4 x i64> %n1, <4 x i64> %a
92  %n2 = sub <4 x i64> zeroinitializer, %a1
93  %b2 = icmp sgt <4 x i64> %a1, zeroinitializer
94  %a2 = select <4 x i1> %b2, <4 x i64> %a1, <4 x i64> %n2
95  ret <4 x i64> %a2
96}
97
98; fold (abs x) -> x iff not-negative
99define <16 x i8> @combine_v16i8_abs_constant(<16 x i8> %a) {
100; CHECK-LABEL: combine_v16i8_abs_constant:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    vandps {{.*}}(%rip), %xmm0, %xmm0
103; CHECK-NEXT:    retq
104  %1 = insertelement <16 x i8> undef, i8 15, i32 0
105  %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
106  %3 = and <16 x i8> %a, %2
107  %4 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %3)
108  ret <16 x i8> %4
109}
110
111define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) {
112; CHECK-LABEL: combine_v8i32_abs_pos:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vpsrld $1, %ymm0, %ymm0
115; CHECK-NEXT:    retq
116  %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
117  %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1)
118  ret <8 x i32> %2
119}
120
121declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone
122declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone
123declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone
124
125declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone
126declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone
127declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone
128