1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx,+sse2 -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=SSE 2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=-avx2,+avx -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefix=AVX 3 4define i32 @cvt_test1(float %a) { 5; SSE-LABEL: cvt_test1 6; SSE: cvttss2si %xmm0, %eax 7; AVX-LABEL: cvt_test1 8; AVX: vcvttss2si %xmm0, %eax 9 %1 = insertelement <4 x float> undef, float %a, i32 0 10 %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1 11 %3 = insertelement <4 x float> %2, float 0.000000e+00, i32 2 12 %4 = insertelement <4 x float> %3, float 0.000000e+00, i32 3 13 %5 = call i32 @llvm.x86.sse.cvttss2si(<4 x float> %4) 14 ret i32 %5 15} 16declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone 17 18define i64 @cvt_test2(float %a) { 19; SSE-LABEL: cvt_test2 20; SSE: cvttss2si %xmm0, %rax 21; AVX-LABEL: cvt_test2 22; AVX: vcvttss2si %xmm0, %rax 23 %1 = insertelement <4 x float> undef, float %a, i32 0 24 %2 = insertelement <4 x float> %1, float 0.000000e+00, i32 1 25 %3 = insertelement <4 x float> %2, float 0.000000e+00, i32 2 26 %4 = insertelement <4 x float> %3, float 0.000000e+00, i32 3 27 %5 = call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %4) 28 ret i64 %5 29} 30declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone 31 32define i32 @cvt_test3(double %a) { 33; SSE-LABEL: cvt_test3 34; SSE: cvttsd2si %xmm0, %eax 35; AVX-LABEL: cvt_test3 36; AVX: vcvttsd2si %xmm0, %eax 37 %1 = insertelement <2 x double> undef, double %a, i32 0 38 %2 = insertelement <2 x double> %1, double 0.000000e+00, i32 1 39 %3 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %2) 40 ret i32 %3 41} 42declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone 43 44define i64 @cvt_test4(double %a) { 45; SSE-LABEL: cvt_test4 46; SSE: cvttsd2si %xmm0, %rax 47; AVX-LABEL: cvt_test4 48; AVX: vcvttsd2si %xmm0, %rax 49 %1 = insertelement <2 x double> undef, double %a, i32 0 50 %2 = insertelement <2 x double> %1, double 0.000000e+00, i32 1 51 %3 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %2) 52 ret i64 %3 53} 54declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone 55