1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+movbe | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=atom | FileCheck %s --check-prefix=CHECK --check-prefix=ATOM 4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=slm | FileCheck %s --check-prefix=CHECK --check-prefix=SLM 5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=haswell | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL 6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=broadwell | FileCheck %s --check-prefix=CHECK --check-prefix=BROADWELL 7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skylake | FileCheck %s --check-prefix=CHECK --check-prefix=SKYLAKE 8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=knl | FileCheck %s --check-prefix=CHECK --check-prefix=HASWELL 9; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=btver2 | FileCheck %s --check-prefix=CHECK --check-prefix=BTVER2 10; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=CHECK --check-prefix=ZNVER1 11 12define i16 @test_movbe_i16(i16 *%a0, i16 %a1, i16 *%a2) { 13; GENERIC-LABEL: test_movbe_i16: 14; GENERIC: # %bb.0: 15; GENERIC-NEXT: movbew (%rdi), %ax # sched: [6:0.50] 16; GENERIC-NEXT: movbew %si, (%rdx) # sched: [1:1.00] 17; GENERIC-NEXT: retq # sched: [1:1.00] 18; 19; ATOM-LABEL: test_movbe_i16: 20; ATOM: # %bb.0: 21; ATOM-NEXT: movbew (%rdi), %ax # sched: [1:1.00] 22; ATOM-NEXT: movbew %si, (%rdx) # sched: [1:1.00] 23; ATOM-NEXT: nop # sched: [1:0.50] 24; ATOM-NEXT: nop # sched: [1:0.50] 25; ATOM-NEXT: nop # sched: [1:0.50] 26; ATOM-NEXT: nop # sched: [1:0.50] 27; ATOM-NEXT: retq # sched: [79:39.50] 28; 29; SLM-LABEL: test_movbe_i16: 30; SLM: # %bb.0: 31; SLM-NEXT: movbew (%rdi), %ax # sched: [4:1.00] 32; SLM-NEXT: movbew %si, (%rdx) # sched: [1:1.00] 33; SLM-NEXT: retq # sched: [4:1.00] 34; 35; HASWELL-LABEL: test_movbe_i16: 36; HASWELL: # %bb.0: 37; HASWELL-NEXT: movbew (%rdi), %ax # sched: [6:0.50] 38; HASWELL-NEXT: movbew %si, (%rdx) # sched: [2:1.00] 39; HASWELL-NEXT: retq # sched: [7:1.00] 40; 41; BROADWELL-LABEL: test_movbe_i16: 42; BROADWELL: # %bb.0: 43; BROADWELL-NEXT: movbew (%rdi), %ax # sched: [6:0.50] 44; BROADWELL-NEXT: movbew %si, (%rdx) # sched: [2:1.00] 45; BROADWELL-NEXT: retq # sched: [7:1.00] 46; 47; SKYLAKE-LABEL: test_movbe_i16: 48; SKYLAKE: # %bb.0: 49; SKYLAKE-NEXT: movbew (%rdi), %ax # sched: [6:0.50] 50; SKYLAKE-NEXT: movbew %si, (%rdx) # sched: [2:1.00] 51; SKYLAKE-NEXT: retq # sched: [7:1.00] 52; 53; BTVER2-LABEL: test_movbe_i16: 54; BTVER2: # %bb.0: 55; BTVER2-NEXT: movbew (%rdi), %ax # sched: [4:1.00] 56; BTVER2-NEXT: movbew %si, (%rdx) # sched: [1:1.00] 57; BTVER2-NEXT: retq # sched: [4:1.00] 58; 59; ZNVER1-LABEL: test_movbe_i16: 60; ZNVER1: # %bb.0: 61; ZNVER1-NEXT: movbew (%rdi), %ax # sched: [5:0.50] 62; ZNVER1-NEXT: movbew %si, (%rdx) # sched: [5:0.50] 63; ZNVER1-NEXT: retq # sched: [1:0.50] 64 %1 = load i16, i16 *%a0 65 %2 = tail call i16 @llvm.bswap.i16( i16 %1 ) 66 %3 = tail call i16 @llvm.bswap.i16( i16 %a1 ) 67 store i16 %3, i16* %a2, align 2 68 ret i16 %2 69} 70declare i16 @llvm.bswap.i16(i16) 71 72define i32 @test_movbe_i32(i32 *%a0, i32 %a1, i32 *%a2) { 73; GENERIC-LABEL: test_movbe_i32: 74; GENERIC: # %bb.0: 75; GENERIC-NEXT: movbel (%rdi), %eax # sched: [6:0.50] 76; GENERIC-NEXT: movbel %esi, (%rdx) # sched: [1:1.00] 77; GENERIC-NEXT: retq # sched: [1:1.00] 78; 79; ATOM-LABEL: test_movbe_i32: 80; ATOM: # %bb.0: 81; ATOM-NEXT: movbel (%rdi), %eax # sched: [1:1.00] 82; ATOM-NEXT: movbel %esi, (%rdx) # sched: [1:1.00] 83; ATOM-NEXT: nop # sched: [1:0.50] 84; ATOM-NEXT: nop # sched: [1:0.50] 85; ATOM-NEXT: nop # sched: [1:0.50] 86; ATOM-NEXT: nop # sched: [1:0.50] 87; ATOM-NEXT: retq # sched: [79:39.50] 88; 89; SLM-LABEL: test_movbe_i32: 90; SLM: # %bb.0: 91; SLM-NEXT: movbel (%rdi), %eax # sched: [4:1.00] 92; SLM-NEXT: movbel %esi, (%rdx) # sched: [1:1.00] 93; SLM-NEXT: retq # sched: [4:1.00] 94; 95; HASWELL-LABEL: test_movbe_i32: 96; HASWELL: # %bb.0: 97; HASWELL-NEXT: movbel (%rdi), %eax # sched: [6:0.50] 98; HASWELL-NEXT: movbel %esi, (%rdx) # sched: [2:1.00] 99; HASWELL-NEXT: retq # sched: [7:1.00] 100; 101; BROADWELL-LABEL: test_movbe_i32: 102; BROADWELL: # %bb.0: 103; BROADWELL-NEXT: movbel (%rdi), %eax # sched: [6:0.50] 104; BROADWELL-NEXT: movbel %esi, (%rdx) # sched: [2:1.00] 105; BROADWELL-NEXT: retq # sched: [7:1.00] 106; 107; SKYLAKE-LABEL: test_movbe_i32: 108; SKYLAKE: # %bb.0: 109; SKYLAKE-NEXT: movbel (%rdi), %eax # sched: [6:0.50] 110; SKYLAKE-NEXT: movbel %esi, (%rdx) # sched: [2:1.00] 111; SKYLAKE-NEXT: retq # sched: [7:1.00] 112; 113; BTVER2-LABEL: test_movbe_i32: 114; BTVER2: # %bb.0: 115; BTVER2-NEXT: movbel (%rdi), %eax # sched: [4:1.00] 116; BTVER2-NEXT: movbel %esi, (%rdx) # sched: [1:1.00] 117; BTVER2-NEXT: retq # sched: [4:1.00] 118; 119; ZNVER1-LABEL: test_movbe_i32: 120; ZNVER1: # %bb.0: 121; ZNVER1-NEXT: movbel (%rdi), %eax # sched: [5:0.50] 122; ZNVER1-NEXT: movbel %esi, (%rdx) # sched: [5:0.50] 123; ZNVER1-NEXT: retq # sched: [1:0.50] 124 %1 = load i32, i32 *%a0 125 %2 = tail call i32 @llvm.bswap.i32( i32 %1 ) 126 %3 = tail call i32 @llvm.bswap.i32( i32 %a1 ) 127 store i32 %3, i32* %a2, align 2 128 ret i32 %2 129} 130declare i32 @llvm.bswap.i32(i32) 131 132define i64 @test_movbe_i64(i64 *%a0, i64 %a1, i64 *%a2) { 133; GENERIC-LABEL: test_movbe_i64: 134; GENERIC: # %bb.0: 135; GENERIC-NEXT: movbeq (%rdi), %rax # sched: [6:0.50] 136; GENERIC-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00] 137; GENERIC-NEXT: retq # sched: [1:1.00] 138; 139; ATOM-LABEL: test_movbe_i64: 140; ATOM: # %bb.0: 141; ATOM-NEXT: movbeq (%rdi), %rax # sched: [1:1.00] 142; ATOM-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00] 143; ATOM-NEXT: nop # sched: [1:0.50] 144; ATOM-NEXT: nop # sched: [1:0.50] 145; ATOM-NEXT: nop # sched: [1:0.50] 146; ATOM-NEXT: nop # sched: [1:0.50] 147; ATOM-NEXT: retq # sched: [79:39.50] 148; 149; SLM-LABEL: test_movbe_i64: 150; SLM: # %bb.0: 151; SLM-NEXT: movbeq (%rdi), %rax # sched: [4:1.00] 152; SLM-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00] 153; SLM-NEXT: retq # sched: [4:1.00] 154; 155; HASWELL-LABEL: test_movbe_i64: 156; HASWELL: # %bb.0: 157; HASWELL-NEXT: movbeq (%rdi), %rax # sched: [6:0.50] 158; HASWELL-NEXT: movbeq %rsi, (%rdx) # sched: [2:1.00] 159; HASWELL-NEXT: retq # sched: [7:1.00] 160; 161; BROADWELL-LABEL: test_movbe_i64: 162; BROADWELL: # %bb.0: 163; BROADWELL-NEXT: movbeq (%rdi), %rax # sched: [6:0.50] 164; BROADWELL-NEXT: movbeq %rsi, (%rdx) # sched: [2:1.00] 165; BROADWELL-NEXT: retq # sched: [7:1.00] 166; 167; SKYLAKE-LABEL: test_movbe_i64: 168; SKYLAKE: # %bb.0: 169; SKYLAKE-NEXT: movbeq (%rdi), %rax # sched: [6:0.50] 170; SKYLAKE-NEXT: movbeq %rsi, (%rdx) # sched: [2:1.00] 171; SKYLAKE-NEXT: retq # sched: [7:1.00] 172; 173; BTVER2-LABEL: test_movbe_i64: 174; BTVER2: # %bb.0: 175; BTVER2-NEXT: movbeq (%rdi), %rax # sched: [4:1.00] 176; BTVER2-NEXT: movbeq %rsi, (%rdx) # sched: [1:1.00] 177; BTVER2-NEXT: retq # sched: [4:1.00] 178; 179; ZNVER1-LABEL: test_movbe_i64: 180; ZNVER1: # %bb.0: 181; ZNVER1-NEXT: movbeq (%rdi), %rax # sched: [5:0.50] 182; ZNVER1-NEXT: movbeq %rsi, (%rdx) # sched: [5:0.50] 183; ZNVER1-NEXT: retq # sched: [1:0.50] 184 %1 = load i64, i64 *%a0 185 %2 = tail call i64 @llvm.bswap.i64( i64 %1 ) 186 %3 = tail call i64 @llvm.bswap.i64( i64 %a1 ) 187 store i64 %3, i64* %a2, align 2 188 ret i64 %2 189} 190declare i64 @llvm.bswap.i64(i64) 191