• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4define i32 @negate_nuw(i32 %x) {
5; CHECK-LABEL: negate_nuw:
6; CHECK:       # %bb.0:
7; CHECK-NEXT:    xorl %eax, %eax
8; CHECK-NEXT:    retq
9  %neg = sub nuw i32 0, %x
10  ret i32 %neg
11}
12
13define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
14; CHECK-LABEL: negate_nuw_vec:
15; CHECK:       # %bb.0:
16; CHECK-NEXT:    xorps %xmm0, %xmm0
17; CHECK-NEXT:    retq
18  %neg = sub nuw <4 x i32> zeroinitializer, %x
19  ret <4 x i32> %neg
20}
21
22define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
23; CHECK-LABEL: negate_zero_or_minsigned_nsw:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    xorl %eax, %eax
26; CHECK-NEXT:    retq
27  %signbit = and i8 %x, 128
28  %neg = sub nsw i8 0, %signbit
29  ret i8 %neg
30}
31
32define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) {
33; CHECK-LABEL: negate_zero_or_minsigned_nsw_vec:
34; CHECK:       # %bb.0:
35; CHECK-NEXT:    xorps %xmm0, %xmm0
36; CHECK-NEXT:    retq
37  %signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
38  %neg = sub nsw <4 x i32> zeroinitializer, %signbit
39  ret <4 x i32> %neg
40}
41
42define i8 @negate_zero_or_minsigned(i8 %x) {
43; CHECK-LABEL: negate_zero_or_minsigned:
44; CHECK:       # %bb.0:
45; CHECK-NEXT:    shlb $7, %dil
46; CHECK-NEXT:    movl %edi, %eax
47; CHECK-NEXT:    retq
48  %signbit = shl i8 %x, 7
49  %neg = sub i8 0, %signbit
50  ret i8 %neg
51}
52
53define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
54; CHECK-LABEL: negate_zero_or_minsigned_vec:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    andps {{.*}}(%rip), %xmm0
57; CHECK-NEXT:    retq
58  %signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
59  %neg = sub <4 x i32> zeroinitializer, %signbit
60  ret <4 x i32> %neg
61}
62
63