1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3 4target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-apple-macosx10.12.0" 6 7@a = common local_unnamed_addr global i16 0, align 4 8@b = common local_unnamed_addr global i16 0, align 4 9 10define i32 @PR32420() { 11; CHECK-LABEL: PR32420: 12; CHECK: ## %bb.0: 13; CHECK-NEXT: movq _a@{{.*}}(%rip), %rcx 14; CHECK-NEXT: movzwl (%rcx), %eax 15; CHECK-NEXT: movl %eax, %edx 16; CHECK-NEXT: shll $12, %edx 17; CHECK-NEXT: sarw $12, %dx 18; CHECK-NEXT: movq _b@{{.*}}(%rip), %rsi 19; CHECK-NEXT: orw (%rsi), %dx 20; CHECK-NEXT: movl (%rcx), %ecx 21; CHECK-NEXT: shll $12, %ecx 22; CHECK-NEXT: sarw $12, %cx 23; CHECK-NEXT: andl %edx, %ecx 24; CHECK-NEXT: movw %cx, (%rsi) 25; CHECK-NEXT: retq 26 %load2 = load i16, i16* @a, align 4 27 %shl3 = shl i16 %load2, 12 28 %ashr4 = ashr i16 %shl3, 12 29 %t2 = load volatile i16, i16* @b, align 4 30 %conv8 = or i16 %t2, %ashr4 31 %load9 = load i16, i16* @a, align 4 32 %shl10 = shl i16 %load9, 12 33 %ashr11 = ashr i16 %shl10, 12 34 %and = and i16 %conv8, %ashr11 35 store i16 %and, i16* @b, align 4 36 %cast1629 = zext i16 %load2 to i32 37 ret i32 %cast1629 38} 39