1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=haswell | FileCheck %s --check-prefix=HSW 3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver1 | FileCheck %s --check-prefix=ZN 4 5define void @_Z15uint64_to_asciimPc(i64 %arg) { 6; HSW-LABEL: _Z15uint64_to_asciimPc: 7; HSW: # %bb.0: # %bb 8; HSW-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81 9; HSW-NEXT: movq %rdi, %rdx 10; HSW-NEXT: mulxq %rax, %rax, %rcx 11; HSW-NEXT: shrq $42, %rcx 12; HSW-NEXT: imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1 13; HSW-NEXT: shrq $20, %rax 14; HSW-NEXT: leal (%rax,%rax,4), %eax 15; HSW-NEXT: addl $5, %eax 16; HSW-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF 17; HSW-NEXT: leal (%rax,%rax,4), %eax 18; HSW-NEXT: shrl $26, %eax 19; HSW-NEXT: orb $48, %al 20; HSW-NEXT: movb %al, (%rax) 21; HSW-NEXT: retq 22; 23; ZN-LABEL: _Z15uint64_to_asciimPc: 24; ZN: # %bb.0: # %bb 25; ZN-NEXT: movabsq $811296384146066817, %rax # imm = 0xB424DC35095CD81 26; ZN-NEXT: movq %rdi, %rdx 27; ZN-NEXT: mulxq %rax, %rax, %rcx 28; ZN-NEXT: shrq $42, %rcx 29; ZN-NEXT: imulq $281474977, %rcx, %rax # imm = 0x10C6F7A1 30; ZN-NEXT: shrq $20, %rax 31; ZN-NEXT: leal 5(%rax,%rax,4), %eax 32; ZN-NEXT: andl $134217727, %eax # imm = 0x7FFFFFF 33; ZN-NEXT: leal (%rax,%rax,4), %eax 34; ZN-NEXT: shrl $26, %eax 35; ZN-NEXT: orb $48, %al 36; ZN-NEXT: movb %al, (%rax) 37; ZN-NEXT: retq 38bb: 39 %tmp = udiv i64 %arg, 100000000000000 40 %tmp1 = mul nuw nsw i64 %tmp, 281474977 41 %tmp2 = lshr i64 %tmp1, 20 42 %tmp3 = trunc i64 %tmp2 to i32 43 %tmp4 = add nuw nsw i32 %tmp3, 1 44 %tmp5 = and i32 %tmp4, 268435455 45 %tmp6 = mul nuw nsw i32 %tmp5, 5 46 %tmp7 = and i32 %tmp6, 134217727 47 %tmp8 = mul nuw nsw i32 %tmp7, 5 48 %tmp9 = lshr i32 %tmp8, 26 49 %tmp10 = trunc i32 %tmp9 to i8 50 %tmp11 = or i8 %tmp10, 48 51 store i8 %tmp11, i8* undef, align 1 52 ret void 53} 54