1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s 3; rdar://7329206 4 5; Use sbb x, x to materialize carry bit in a GPR. The value is either 6; all 1's or all 0's. 7 8define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp { 9; CHECK-LABEL: t1: 10; CHECK: ## %bb.0: 11; CHECK-NEXT: xorl %eax, %eax 12; CHECK-NEXT: cmpl $26, %edi 13; CHECK-NEXT: seta %al 14; CHECK-NEXT: shll $5, %eax 15; CHECK-NEXT: retq 16 %t0 = icmp ugt i16 %x, 26 17 %if = select i1 %t0, i16 32, i16 0 18 ret i16 %if 19} 20 21define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp { 22; CHECK-LABEL: t2: 23; CHECK: ## %bb.0: 24; CHECK-NEXT: xorl %eax, %eax 25; CHECK-NEXT: cmpl $26, %edi 26; CHECK-NEXT: setb %al 27; CHECK-NEXT: shll $5, %eax 28; CHECK-NEXT: retq 29 %t0 = icmp ult i16 %x, 26 30 %if = select i1 %t0, i16 32, i16 0 31 ret i16 %if 32} 33 34define i64 @t3(i64 %x) nounwind readnone ssp { 35; CHECK-LABEL: t3: 36; CHECK: ## %bb.0: 37; CHECK-NEXT: xorl %eax, %eax 38; CHECK-NEXT: cmpq $18, %rdi 39; CHECK-NEXT: setb %al 40; CHECK-NEXT: shlq $6, %rax 41; CHECK-NEXT: retq 42 %t0 = icmp ult i64 %x, 18 43 %if = select i1 %t0, i64 64, i64 0 44 ret i64 %if 45} 46 47@v4 = common global i32 0, align 4 48 49define i32 @t4(i32 %a) { 50; CHECK-LABEL: t4: 51; CHECK: ## %bb.0: 52; CHECK-NEXT: movq _v4@{{.*}}(%rip), %rax 53; CHECK-NEXT: cmpl $1, (%rax) 54; CHECK-NEXT: movw $1, %ax 55; CHECK-NEXT: adcw $0, %ax 56; CHECK-NEXT: shll $16, %eax 57; CHECK-NEXT: retq 58 %t0 = load i32, i32* @v4, align 4 59 %not.tobool = icmp eq i32 %t0, 0 60 %conv.i = sext i1 %not.tobool to i16 61 %call.lobit = lshr i16 %conv.i, 15 62 %add.i.1 = add nuw nsw i16 %call.lobit, 1 63 %conv4.2 = zext i16 %add.i.1 to i32 64 %add = shl nuw nsw i32 %conv4.2, 16 65 ret i32 %add 66} 67 68define i8 @t5(i32 %a) #0 { 69; CHECK-LABEL: t5: 70; CHECK: ## %bb.0: 71; CHECK-NEXT: testl %edi, %edi 72; CHECK-NEXT: setns %al 73; CHECK-NEXT: retq 74 %.lobit = lshr i32 %a, 31 75 %trunc = trunc i32 %.lobit to i8 76 %.not = xor i8 %trunc, 1 77 ret i8 %.not 78} 79 80define zeroext i1 @t6(i32 %a) #0 { 81; CHECK-LABEL: t6: 82; CHECK: ## %bb.0: 83; CHECK-NEXT: testl %edi, %edi 84; CHECK-NEXT: setns %al 85; CHECK-NEXT: retq 86 %.lobit = lshr i32 %a, 31 87 %trunc = trunc i32 %.lobit to i1 88 %.not = xor i1 %trunc, 1 89 ret i1 %.not 90} 91 92attributes #0 = { "target-cpu"="skylake-avx512" } 93