1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s 3 4; If positive... 5 6define i32 @zext_ifpos(i32 %x) { 7; CHECK-LABEL: zext_ifpos: 8; CHECK: # %bb.0: 9; CHECK-NEXT: notl %edi 10; CHECK-NEXT: shrl $31, %edi 11; CHECK-NEXT: movl %edi, %eax 12; CHECK-NEXT: retq 13 %c = icmp sgt i32 %x, -1 14 %e = zext i1 %c to i32 15 ret i32 %e 16} 17 18define i32 @add_zext_ifpos(i32 %x) { 19; CHECK-LABEL: add_zext_ifpos: 20; CHECK: # %bb.0: 21; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 22; CHECK-NEXT: sarl $31, %edi 23; CHECK-NEXT: leal 42(%rdi), %eax 24; CHECK-NEXT: retq 25 %c = icmp sgt i32 %x, -1 26 %e = zext i1 %c to i32 27 %r = add i32 %e, 41 28 ret i32 %r 29} 30 31define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) { 32; CHECK-LABEL: add_zext_ifpos_vec_splat: 33; CHECK: # %bb.0: 34; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 35; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 36; CHECK-NEXT: psrld $31, %xmm0 37; CHECK-NEXT: por {{.*}}(%rip), %xmm0 38; CHECK-NEXT: retq 39 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 40 %e = zext <4 x i1> %c to <4 x i32> 41 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> 42 ret <4 x i32> %r 43} 44 45define i32 @sel_ifpos_tval_bigger(i32 %x) { 46; CHECK-LABEL: sel_ifpos_tval_bigger: 47; CHECK: # %bb.0: 48; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 49; CHECK-NEXT: sarl $31, %edi 50; CHECK-NEXT: leal 42(%rdi), %eax 51; CHECK-NEXT: retq 52 %c = icmp sgt i32 %x, -1 53 %r = select i1 %c, i32 42, i32 41 54 ret i32 %r 55} 56 57define i32 @sext_ifpos(i32 %x) { 58; CHECK-LABEL: sext_ifpos: 59; CHECK: # %bb.0: 60; CHECK-NEXT: notl %edi 61; CHECK-NEXT: sarl $31, %edi 62; CHECK-NEXT: movl %edi, %eax 63; CHECK-NEXT: retq 64 %c = icmp sgt i32 %x, -1 65 %e = sext i1 %c to i32 66 ret i32 %e 67} 68 69define i32 @add_sext_ifpos(i32 %x) { 70; CHECK-LABEL: add_sext_ifpos: 71; CHECK: # %bb.0: 72; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 73; CHECK-NEXT: shrl $31, %edi 74; CHECK-NEXT: leal 41(%rdi), %eax 75; CHECK-NEXT: retq 76 %c = icmp sgt i32 %x, -1 77 %e = sext i1 %c to i32 78 %r = add i32 %e, 42 79 ret i32 %r 80} 81 82define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) { 83; CHECK-LABEL: add_sext_ifpos_vec_splat: 84; CHECK: # %bb.0: 85; CHECK-NEXT: pcmpeqd %xmm1, %xmm1 86; CHECK-NEXT: pcmpgtd %xmm1, %xmm0 87; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 88; CHECK-NEXT: retq 89 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 90 %e = sext <4 x i1> %c to <4 x i32> 91 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> 92 ret <4 x i32> %r 93} 94 95define i32 @sel_ifpos_fval_bigger(i32 %x) { 96; CHECK-LABEL: sel_ifpos_fval_bigger: 97; CHECK: # %bb.0: 98; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 99; CHECK-NEXT: shrl $31, %edi 100; CHECK-NEXT: leal 41(%rdi), %eax 101; CHECK-NEXT: retq 102 %c = icmp sgt i32 %x, -1 103 %r = select i1 %c, i32 41, i32 42 104 ret i32 %r 105} 106 107; If negative... 108 109define i32 @zext_ifneg(i32 %x) { 110; CHECK-LABEL: zext_ifneg: 111; CHECK: # %bb.0: 112; CHECK-NEXT: shrl $31, %edi 113; CHECK-NEXT: movl %edi, %eax 114; CHECK-NEXT: retq 115 %c = icmp slt i32 %x, 0 116 %r = zext i1 %c to i32 117 ret i32 %r 118} 119 120define i32 @add_zext_ifneg(i32 %x) { 121; CHECK-LABEL: add_zext_ifneg: 122; CHECK: # %bb.0: 123; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 124; CHECK-NEXT: shrl $31, %edi 125; CHECK-NEXT: leal 41(%rdi), %eax 126; CHECK-NEXT: retq 127 %c = icmp slt i32 %x, 0 128 %e = zext i1 %c to i32 129 %r = add i32 %e, 41 130 ret i32 %r 131} 132 133define i32 @sel_ifneg_tval_bigger(i32 %x) { 134; CHECK-LABEL: sel_ifneg_tval_bigger: 135; CHECK: # %bb.0: 136; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 137; CHECK-NEXT: shrl $31, %edi 138; CHECK-NEXT: leal 41(%rdi), %eax 139; CHECK-NEXT: retq 140 %c = icmp slt i32 %x, 0 141 %r = select i1 %c, i32 42, i32 41 142 ret i32 %r 143} 144 145define i32 @sext_ifneg(i32 %x) { 146; CHECK-LABEL: sext_ifneg: 147; CHECK: # %bb.0: 148; CHECK-NEXT: sarl $31, %edi 149; CHECK-NEXT: movl %edi, %eax 150; CHECK-NEXT: retq 151 %c = icmp slt i32 %x, 0 152 %r = sext i1 %c to i32 153 ret i32 %r 154} 155 156define i32 @add_sext_ifneg(i32 %x) { 157; CHECK-LABEL: add_sext_ifneg: 158; CHECK: # %bb.0: 159; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 160; CHECK-NEXT: sarl $31, %edi 161; CHECK-NEXT: leal 42(%rdi), %eax 162; CHECK-NEXT: retq 163 %c = icmp slt i32 %x, 0 164 %e = sext i1 %c to i32 165 %r = add i32 %e, 42 166 ret i32 %r 167} 168 169define i32 @sel_ifneg_fval_bigger(i32 %x) { 170; CHECK-LABEL: sel_ifneg_fval_bigger: 171; CHECK: # %bb.0: 172; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 173; CHECK-NEXT: sarl $31, %edi 174; CHECK-NEXT: leal 42(%rdi), %eax 175; CHECK-NEXT: retq 176 %c = icmp slt i32 %x, 0 177 %r = select i1 %c, i32 41, i32 42 178 ret i32 %r 179} 180 181define i32 @add_lshr_not(i32 %x) { 182; CHECK-LABEL: add_lshr_not: 183; CHECK: # %bb.0: 184; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 185; CHECK-NEXT: sarl $31, %edi 186; CHECK-NEXT: leal 42(%rdi), %eax 187; CHECK-NEXT: retq 188 %not = xor i32 %x, -1 189 %sh = lshr i32 %not, 31 190 %r = add i32 %sh, 41 191 ret i32 %r 192} 193 194define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) { 195; CHECK-LABEL: add_lshr_not_vec_splat: 196; CHECK: # %bb.0: 197; CHECK-NEXT: psrad $31, %xmm0 198; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 199; CHECK-NEXT: retq 200 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 201 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> 202 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> 203 ret <4 x i32> %r 204} 205 206define i32 @sub_lshr_not(i32 %x) { 207; CHECK-LABEL: sub_lshr_not: 208; CHECK: # %bb.0: 209; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 210; CHECK-NEXT: shrl $31, %edi 211; CHECK-NEXT: leal 42(%rdi), %eax 212; CHECK-NEXT: retq 213 %not = xor i32 %x, -1 214 %sh = lshr i32 %not, 31 215 %r = sub i32 43, %sh 216 ret i32 %r 217} 218 219define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) { 220; CHECK-LABEL: sub_lshr_not_vec_splat: 221; CHECK: # %bb.0: 222; CHECK-NEXT: psrld $31, %xmm0 223; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 224; CHECK-NEXT: retq 225 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1> 226 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31> 227 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e 228 ret <4 x i32> %r 229} 230 231define i32 @sub_lshr(i32 %x, i32 %y) { 232; CHECK-LABEL: sub_lshr: 233; CHECK: # %bb.0: 234; CHECK-NEXT: # kill: def $esi killed $esi def $rsi 235; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 236; CHECK-NEXT: sarl $31, %edi 237; CHECK-NEXT: leal (%rdi,%rsi), %eax 238; CHECK-NEXT: retq 239 %sh = lshr i32 %x, 31 240 %r = sub i32 %y, %sh 241 ret i32 %r 242} 243 244define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) { 245; CHECK-LABEL: sub_lshr_vec: 246; CHECK: # %bb.0: 247; CHECK-NEXT: psrad $31, %xmm0 248; CHECK-NEXT: paddd %xmm1, %xmm0 249; CHECK-NEXT: retq 250 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> 251 %r = sub <4 x i32> %y, %sh 252 ret <4 x i32> %r 253} 254 255define i32 @sub_const_op_lshr(i32 %x) { 256; CHECK-LABEL: sub_const_op_lshr: 257; CHECK: # %bb.0: 258; CHECK-NEXT: # kill: def $edi killed $edi def $rdi 259; CHECK-NEXT: sarl $31, %edi 260; CHECK-NEXT: leal 43(%rdi), %eax 261; CHECK-NEXT: retq 262 %sh = lshr i32 %x, 31 263 %r = sub i32 43, %sh 264 ret i32 %r 265} 266 267define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) { 268; CHECK-LABEL: sub_const_op_lshr_vec: 269; CHECK: # %bb.0: 270; CHECK-NEXT: psrad $31, %xmm0 271; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0 272; CHECK-NEXT: retq 273 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31> 274 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh 275 ret <4 x i32> %r 276} 277 278