1# RUN: not llvm-mc -disassemble -triple armv8a-none-eabi -mattr=+fullfp16,+neon -show-encoding < %s 2>%t | FileCheck %s 2# RUN FileCheck %s < %t --check-prefix=STDERR 3 4# CHECK: vadd.f16 d0, d1, d2 5# CHECK: vadd.f16 q0, q1, q2 6[0x02,0x0d,0x11,0xf2] 7[0x44,0x0d,0x12,0xf2] 8 9# CHECK: vsub.f16 d0, d1, d2 10# CHECK: vsub.f16 q0, q1, q2 11[0x02,0x0d,0x31,0xf2] 12[0x44,0x0d,0x32,0xf2] 13 14# CHECK: vmul.f16 d0, d1, d2 15# CHECK: vmul.f16 q0, q1, q2 16[0x12,0x0d,0x11,0xf3] 17[0x54,0x0d,0x12,0xf3] 18 19# CHECK: vmul.f16 d1, d2, d3[2] 20# CHECK: vmul.f16 q4, q5, d6[3] 21[0x63,0x19,0x92,0xf2] 22[0x6e,0x89,0x9a,0xf3] 23 24# CHECK: vmla.f16 d0, d1, d2 25# CHECK: vmla.f16 q0, q1, q2 26[0x12,0x0d,0x11,0xf2] 27[0x54,0x0d,0x12,0xf2] 28 29# CHECK: vmla.f16 d5, d6, d7[2] 30# CHECK: vmla.f16 q5, q6, d7[3] 31[0x67,0x51,0x96,0xf2] 32[0x6f,0xa1,0x9c,0xf3] 33 34# CHECK: vmls.f16 d0, d1, d2 35# CHECK: vmls.f16 q0, q1, q2 36[0x12,0x0d,0x31,0xf2] 37[0x54,0x0d,0x32,0xf2] 38 39# CHECK: vmls.f16 d5, d6, d7[2] 40# CHECK: vmls.f16 q5, q6, d7[3] 41[0x67,0x55,0x96,0xf2] 42[0x6f,0xa5,0x9c,0xf3] 43 44# CHECK: vfma.f16 d0, d1, d2 45# CHECK: vfma.f16 q0, q1, q2 46[0x12,0x0c,0x11,0xf2] 47[0x54,0x0c,0x12,0xf2] 48 49# CHECK: vfms.f16 d0, d1, d2 50# CHECK: vfms.f16 q0, q1, q2 51[0x12,0x0c,0x31,0xf2] 52[0x54,0x0c,0x32,0xf2] 53 54# CHECK: vceq.f16 d2, d3, d4 55# CHECK: vceq.f16 q2, q3, q4 56[0x04,0x2e,0x13,0xf2] 57[0x48,0x4e,0x16,0xf2] 58 59# CHECK: vceq.f16 d2, d3, #0 60# CHECK: vceq.f16 q2, q3, #0 61[0x03,0x25,0xb5,0xf3] 62[0x46,0x45,0xb5,0xf3] 63 64# CHECK: vcge.f16 d2, d3, d4 65# CHECK: vcge.f16 q2, q3, q4 66[0x04,0x2e,0x13,0xf3] 67[0x48,0x4e,0x16,0xf3] 68 69# CHECK: vcge.f16 d2, d3, #0 70# CHECK: vcge.f16 q2, q3, #0 71[0x83,0x24,0xb5,0xf3] 72[0xc6,0x44,0xb5,0xf3] 73 74# CHECK: vcgt.f16 d2, d3, d4 75# CHECK: vcgt.f16 q2, q3, q4 76[0x04,0x2e,0x33,0xf3] 77[0x48,0x4e,0x36,0xf3] 78 79# CHECK: vcgt.f16 d2, d3, #0 80# CHECK: vcgt.f16 q2, q3, #0 81[0x03,0x24,0xb5,0xf3] 82[0x46,0x44,0xb5,0xf3] 83 84# CHECK: vcle.f16 d2, d3, #0 85# CHECK: vcle.f16 q2, q3, #0 86[0x83,0x25,0xb5,0xf3] 87[0xc6,0x45,0xb5,0xf3] 88 89# CHECK: vclt.f16 d2, d3, #0 90# CHECK: vclt.f16 q2, q3, #0 91[0x03,0x26,0xb5,0xf3] 92[0x46,0x46,0xb5,0xf3] 93 94# CHECK: vacge.f16 d0, d1, d2 95# CHECK: vacge.f16 q0, q1, q2 96[0x12,0x0e,0x11,0xf3] 97[0x54,0x0e,0x12,0xf3] 98 99# CHECK: vacgt.f16 d0, d1, d2 100# CHECK: vacgt.f16 q0, q1, q2 101[0x12,0x0e,0x31,0xf3] 102[0x54,0x0e,0x32,0xf3] 103 104# CHECK: vabd.f16 d0, d1, d2 105# CHECK: vabd.f16 q0, q1, q2 106[0x02,0x0d,0x31,0xf3] 107[0x44,0x0d,0x32,0xf3] 108 109# CHECK: vabs.f16 d0, d1 110# CHECK: vabs.f16 q0, q1 111[0x01,0x07,0xb5,0xf3] 112[0x42,0x07,0xb5,0xf3] 113 114# CHECK: vmax.f16 d0, d1, d2 115# CHECK: vmax.f16 q0, q1, q2 116[0x02,0x0f,0x11,0xf2] 117[0x44,0x0f,0x12,0xf2] 118 119# CHECK: vmin.f16 d0, d1, d2 120# CHECK: vmin.f16 q0, q1, q2 121[0x02,0x0f,0x31,0xf2] 122[0x44,0x0f,0x32,0xf2] 123 124# CHECK: vmaxnm.f16 d0, d1, d2 125# CHECK: vmaxnm.f16 q0, q1, q2 126[0x12,0x0f,0x11,0xf3] 127[0x54,0x0f,0x12,0xf3] 128 129# CHECK: vminnm.f16 d0, d1, d2 130# CHECK: vminnm.f16 q0, q1, q2 131[0x12,0x0f,0x31,0xf3] 132[0x54,0x0f,0x32,0xf3] 133 134# CHECK: vpadd.f16 d0, d1, d2 135[0x02,0x0d,0x11,0xf3] 136 137# CHECK: vpmax.f16 d0, d1, d2 138[0x02,0x0f,0x11,0xf3] 139 140# CHECK: vpmin.f16 d0, d1, d2 141[0x02,0x0f,0x31,0xf3] 142 143# CHECK: vrecpe.f16 d0, d1 144# CHECK: vrecpe.f16 q0, q1 145[0x01,0x05,0xb7,0xf3] 146[0x42,0x05,0xb7,0xf3] 147 148# CHECK: vrecps.f16 d0, d1, d2 149# CHECK: vrecps.f16 q0, q1, q2 150[0x12,0x0f,0x11,0xf2] 151[0x54,0x0f,0x12,0xf2] 152 153# CHECK: vrsqrte.f16 d0, d1 154# CHECK: vrsqrte.f16 q0, q1 155[0x81,0x05,0xb7,0xf3] 156[0xc2,0x05,0xb7,0xf3] 157 158# CHECK: vrsqrts.f16 d0, d1, d2 159# CHECK: vrsqrts.f16 q0, q1, q2 160[0x12,0x0f,0x31,0xf2] 161[0x54,0x0f,0x32,0xf2] 162 163# CHECK: vneg.f16 d0, d1 164# CHECK: vneg.f16 q0, q1 165[0x81,0x07,0xb5,0xf3] 166[0xc2,0x07,0xb5,0xf3] 167 168# CHECK: vcvt.s16.f16 d0, d1 169# CHECK: vcvt.u16.f16 d0, d1 170# CHECK: vcvt.f16.s16 d0, d1 171# CHECK: vcvt.f16.u16 d0, d1 172# CHECK: vcvt.s16.f16 q0, q1 173# CHECK: vcvt.u16.f16 q0, q1 174# CHECK: vcvt.f16.s16 q0, q1 175# CHECK: vcvt.f16.u16 q0, q1 176[0x01,0x07,0xb7,0xf3] 177[0x81,0x07,0xb7,0xf3] 178[0x01,0x06,0xb7,0xf3] 179[0x81,0x06,0xb7,0xf3] 180[0x42,0x07,0xb7,0xf3] 181[0xc2,0x07,0xb7,0xf3] 182[0x42,0x06,0xb7,0xf3] 183[0xc2,0x06,0xb7,0xf3] 184 185# CHECK: vcvta.s16.f16 d0, d1 186# CHECK: vcvta.s16.f16 q0, q1 187# CHECK: vcvta.u16.f16 d0, d1 188# CHECK: vcvta.u16.f16 q0, q1 189[0x01,0x00,0xb7,0xf3] 190[0x42,0x00,0xb7,0xf3] 191[0x81,0x00,0xb7,0xf3] 192[0xc2,0x00,0xb7,0xf3] 193 194# CHECK: vcvtm.s16.f16 d0, d1 195# CHECK: vcvtm.s16.f16 q0, q1 196# CHECK: vcvtm.u16.f16 d0, d1 197# CHECK: vcvtm.u16.f16 q0, q1 198[0x01,0x03,0xb7,0xf3] 199[0x42,0x03,0xb7,0xf3] 200[0x81,0x03,0xb7,0xf3] 201[0xc2,0x03,0xb7,0xf3] 202 203# CHECK: vcvtn.s16.f16 d0, d1 204# CHECK: vcvtn.s16.f16 q0, q1 205# CHECK: vcvtn.u16.f16 d0, d1 206# CHECK: vcvtn.u16.f16 q0, q1 207[0x01,0x01,0xb7,0xf3] 208[0x42,0x01,0xb7,0xf3] 209[0x81,0x01,0xb7,0xf3] 210[0xc2,0x01,0xb7,0xf3] 211 212# CHECK: vcvtp.s16.f16 d0, d1 213# CHECK: vcvtp.s16.f16 q0, q1 214# CHECK: vcvtp.u16.f16 d0, d1 215# CHECK: vcvtp.u16.f16 q0, q1 216[0x01,0x02,0xb7,0xf3] 217[0x42,0x02,0xb7,0xf3] 218[0x81,0x02,0xb7,0xf3] 219[0xc2,0x02,0xb7,0xf3] 220 221# CHECK: vcvt.s16.f16 d0, d1, #1 222# CHECK: vcvt.u16.f16 d0, d1, #2 223# CHECK: vcvt.f16.s16 d0, d1, #3 224# CHECK: vcvt.f16.u16 d0, d1, #4 225# CHECK: vcvt.s16.f16 q0, q1, #5 226# CHECK: vcvt.u16.f16 q0, q1, #6 227# CHECK: vcvt.f16.s16 q0, q1, #7 228# CHECK: vcvt.f16.u16 q0, q1, #8 229[0x11,0x0d,0xbf,0xf2] 230[0x11,0x0d,0xbe,0xf3] 231[0x11,0x0c,0xbd,0xf2] 232[0x11,0x0c,0xbc,0xf3] 233[0x52,0x0d,0xbb,0xf2] 234[0x52,0x0d,0xba,0xf3] 235[0x52,0x0c,0xb9,0xf2] 236[0x52,0x0c,0xb8,0xf3] 237 238# CHECK: vrinta.f16 d0, d1 239# CHECK: vrinta.f16 q0, q1 240[0x01,0x05,0xb6,0xf3] 241[0x42,0x05,0xb6,0xf3] 242 243# CHECK: vrintm.f16 d0, d1 244# CHECK: vrintm.f16 q0, q1 245[0x81,0x06,0xb6,0xf3] 246[0xc2,0x06,0xb6,0xf3] 247 248# CHECK: vrintn.f16 d0, d1 249# CHECK: vrintn.f16 q0, q1 250[0x01,0x04,0xb6,0xf3] 251[0x42,0x04,0xb6,0xf3] 252 253# CHECK: vrintp.f16 d0, d1 254# CHECK: vrintp.f16 q0, q1 255[0x81,0x07,0xb6,0xf3] 256[0xc2,0x07,0xb6,0xf3] 257 258# CHECK: vrintx.f16 d0, d1 259# CHECK: vrintx.f16 q0, q1 260[0x81,0x04,0xb6,0xf3] 261[0xc2,0x04,0xb6,0xf3] 262 263# CHECK: vrintz.f16 d0, d1 264# CHECK: vrintz.f16 q0, q1 265[0x81,0x05,0xb6,0xf3] 266[0xc2,0x05,0xb6,0xf3] 267 268# Existing VMOV(immediate, Advanced SIMD) instructions within the encoding 269# space of the new FP16 VCVT(between floating - point and fixed - point, 270# Advanced SIMD): 271# 4 -- Q 272# 2 -- VMOV op 273# 1 -- VCVT op 274# 2 -- VCVT FP size 275[0x10,0x0c,0xc7,0xf2] 276[0x10,0x0d,0xc7,0xf2] 277[0x10,0x0e,0xc7,0xf2] 278[0x10,0x0f,0xc7,0xf2] 279[0x20,0x0c,0xc7,0xf2] 280[0x20,0x0d,0xc7,0xf2] 281[0x20,0x0e,0xc7,0xf2] 282[0x20,0x0f,0xc7,0xf2] 283[0x50,0x0c,0xc7,0xf2] 284[0x50,0x0d,0xc7,0xf2] 285[0x50,0x0e,0xc7,0xf2] 286[0x50,0x0f,0xc7,0xf2] 287[0x70,0x0c,0xc7,0xf2] 288[0x70,0x0d,0xc7,0xf2] 289[0x70,0x0e,0xc7,0xf2] 290[0x70,0x0f,0xc7,0xf2] 291# CHECK: vmov.i32 d16, #0x70ff 292# CHECK: vmov.i32 d16, #0x70ffff 293# CHECK: vmov.i8 d16, #0x70 294# CHECK: vmov.f32 d16, #1.000000e+00 295# CHECK: vmull.s8 q8, d7, d16 296# STDERR: warning: invalid instruction encoding 297# STDERR-NEXT: [0x20,0x0d,0xc7,0xf2] 298# CHECK: vmull.p8 q8, d7, d16 299# STDERR: warning: invalid instruction encoding 300# STDERR-NEXT: [0x20,0x0f,0xc7,0xf2] 301# CHECK: vmov.i32 q8, #0x70ff 302# CHECK: vmov.i32 q8, #0x70ffff 303# CHECK: vmov.i8 q8, #0x70 304# CHECK: vmov.f32 q8, #1.000000e+00 305# CHECK: vmvn.i32 q8, #0x70ff 306# CHECK: vmvn.i32 q8, #0x70ffff 307# CHECK: vmov.i64 q8, #0xffffff0000000 308# STDERR: warning: invalid instruction encoding 309# STDERR-NEXT: [0x70,0x0f,0xc7,0xf2] 310