1# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py 2# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats=false < %s | FileCheck %s -check-prefix=ALL 3# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL 4# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -all-stats -dispatch-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL 5# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL 6# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -dispatch-stats=false -all-stats < %s | FileCheck %s -check-prefix=ALL -check-prefix=FULL 7 8add %eax, %eax 9 10# ALL: Iterations: 100 11# ALL-NEXT: Instructions: 100 12# ALL-NEXT: Total Cycles: 103 13# ALL-NEXT: Dispatch Width: 2 14# ALL-NEXT: IPC: 0.97 15# ALL-NEXT: Block RThroughput: 0.5 16 17# ALL: Instruction Info: 18# ALL-NEXT: [1]: #uOps 19# ALL-NEXT: [2]: Latency 20# ALL-NEXT: [3]: RThroughput 21# ALL-NEXT: [4]: MayLoad 22# ALL-NEXT: [5]: MayStore 23# ALL-NEXT: [6]: HasSideEffects (U) 24 25# ALL: [1] [2] [3] [4] [5] [6] Instructions: 26# ALL-NEXT: 1 1 0.50 addl %eax, %eax 27 28# FULL: Dynamic Dispatch Stall Cycles: 29# FULL-NEXT: RAT - Register unavailable: 0 30# FULL-NEXT: RCU - Retire tokens unavailable: 0 31# FULL-NEXT: SCHEDQ - Scheduler full: 61 32# FULL-NEXT: LQ - Load queue full: 0 33# FULL-NEXT: SQ - Store queue full: 0 34# FULL-NEXT: GROUP - Static restrictions on the dispatch group: 0 35 36# FULL: Dispatch Logic - number of cycles where we saw N instructions dispatched: 37# FULL-NEXT: [# dispatched], [# cycles] 38# FULL-NEXT: 0, 22 (21.4%) 39# FULL-NEXT: 1, 62 (60.2%) 40# FULL-NEXT: 2, 19 (18.4%) 41 42# FULL: Schedulers - number of cycles where we saw N instructions issued: 43# FULL-NEXT: [# issued], [# cycles] 44# FULL-NEXT: 0, 3 (2.9%) 45# FULL-NEXT: 1, 100 (97.1%) 46 47# FULL: Scheduler's queue usage: 48# FULL-NEXT: JALU01, 20/20 49# FULL-NEXT: JFPU01, 0/18 50# FULL-NEXT: JLSAGU, 0/12 51 52# FULL: Retire Control Unit - number of cycles where we saw N instructions retired: 53# FULL-NEXT: [# retired], [# cycles] 54# FULL-NEXT: 0, 3 (2.9%) 55# FULL-NEXT: 1, 100 (97.1%) 56 57# FULL: Register File statistics: 58# FULL-NEXT: Total number of mappings created: 200 59# FULL-NEXT: Max number of mappings used: 44 60 61# FULL: * Register File #1 -- JFpuPRF: 62# FULL-NEXT: Number of physical registers: 72 63# FULL-NEXT: Total number of mappings created: 0 64# FULL-NEXT: Max number of mappings used: 0 65 66# FULL: * Register File #2 -- JIntegerPRF: 67# FULL-NEXT: Number of physical registers: 64 68# FULL-NEXT: Total number of mappings created: 200 69# FULL-NEXT: Max number of mappings used: 44 70 71# FULL: Resources: 72# FULL-NEXT: [0] - JALU0 73# FULL-NEXT: [1] - JALU1 74# FULL-NEXT: [2] - JDiv 75# FULL-NEXT: [3] - JFPA 76# FULL-NEXT: [4] - JFPM 77# FULL-NEXT: [5] - JFPU0 78# FULL-NEXT: [6] - JFPU1 79# FULL-NEXT: [7] - JLAGU 80# FULL-NEXT: [8] - JMul 81# FULL-NEXT: [9] - JSAGU 82# FULL-NEXT: [10] - JSTC 83# FULL-NEXT: [11] - JVALU0 84# FULL-NEXT: [12] - JVALU1 85# FULL-NEXT: [13] - JVIMUL 86 87# FULL: Resource pressure per iteration: 88# FULL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] 89# FULL-NEXT: 0.50 0.50 - - - - - - - - - - - - 90 91# FULL: Resource pressure by instruction: 92# FULL-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions: 93# FULL-NEXT: 0.50 0.50 - - - - - - - - - - - - addl %eax, %eax 94