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1define <4 x float> @insertelement_v4f32(<4 x float> %vec, float %elt, i32 %idx) {
2  switch i32 %idx, label %abort [
3  i32 0, label %idx0
4  i32 1, label %idx1
5  i32 2, label %idx2
6  i32 3, label %idx3
7  ]
8idx0:
9  %res0 = insertelement <4 x float> %vec, float %elt, i32 0
10  ret <4 x float> %res0
11idx1:
12  %res1 = insertelement <4 x float> %vec, float %elt, i32 1
13  ret <4 x float> %res1
14idx2:
15  %res2 = insertelement <4 x float> %vec, float %elt, i32 2
16  ret <4 x float> %res2
17idx3:
18  %res3 = insertelement <4 x float> %vec, float %elt, i32 3
19  ret <4 x float> %res3
20abort:
21  unreachable
22}
23
24define <4 x i32> @insertelement_v4i1(<4 x i32> %arg_vec, i64 %elt_arg, i32 %idx) {
25  %vec = trunc <4 x i32> %arg_vec to <4 x i1>
26  %elt = trunc i64 %elt_arg to i1
27  switch i32 %idx, label %abort [
28  i32 0, label %idx0
29  i32 1, label %idx1
30  i32 2, label %idx2
31  i32 3, label %idx3
32  ]
33idx0:
34  %res0_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 0
35  %res0 = zext <4 x i1> %res0_i1 to <4 x i32>
36  ret <4 x i32> %res0
37idx1:
38  %res1_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 1
39  %res1 = zext <4 x i1> %res1_i1 to <4 x i32>
40  ret <4 x i32> %res1
41idx2:
42  %res2_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 2
43  %res2 = zext <4 x i1> %res2_i1 to <4 x i32>
44  ret <4 x i32> %res2
45idx3:
46  %res3_i1 = insertelement <4 x i1> %vec, i1 %elt, i32 3
47  %res3 = zext <4 x i1> %res3_i1 to <4 x i32>
48  ret <4 x i32> %res3
49abort:
50  unreachable
51}
52
53define <8 x i16> @insertelement_v8i1(<8 x i16> %arg_vec, i64 %elt_arg, i32 %idx) {
54  %vec = trunc <8 x i16> %arg_vec to <8 x i1>
55  %elt = trunc i64 %elt_arg to i1
56  switch i32 %idx, label %abort [
57  i32 0, label %idx0
58  i32 1, label %idx1
59  i32 2, label %idx2
60  i32 3, label %idx3
61  i32 4, label %idx4
62  i32 5, label %idx5
63  i32 6, label %idx6
64  i32 7, label %idx7
65  ]
66idx0:
67  %res0_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 0
68  %res0 = zext <8 x i1> %res0_i1 to <8 x i16>
69  ret <8 x i16> %res0
70idx1:
71  %res1_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 1
72  %res1 = zext <8 x i1> %res1_i1 to <8 x i16>
73  ret <8 x i16> %res1
74idx2:
75  %res2_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 2
76  %res2 = zext <8 x i1> %res2_i1 to <8 x i16>
77  ret <8 x i16> %res2
78idx3:
79  %res3_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 3
80  %res3 = zext <8 x i1> %res3_i1 to <8 x i16>
81  ret <8 x i16> %res3
82idx4:
83  %res4_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 4
84  %res4 = zext <8 x i1> %res4_i1 to <8 x i16>
85  ret <8 x i16> %res4
86idx5:
87  %res5_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 5
88  %res5 = zext <8 x i1> %res5_i1 to <8 x i16>
89  ret <8 x i16> %res5
90idx6:
91  %res6_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 6
92  %res6 = zext <8 x i1> %res6_i1 to <8 x i16>
93  ret <8 x i16> %res6
94idx7:
95  %res7_i1 = insertelement <8 x i1> %vec, i1 %elt, i32 7
96  %res7 = zext <8 x i1> %res7_i1 to <8 x i16>
97  ret <8 x i16> %res7
98abort:
99  unreachable
100}
101
102define <16 x i8> @insertelement_v16i1(<16 x i8> %arg_vec, i64 %elt_arg, i32 %idx) {
103  %vec = trunc <16 x i8> %arg_vec to <16 x i1>
104  %elt = trunc i64 %elt_arg to i1
105  switch i32 %idx, label %abort [
106  i32 0, label %idx0
107  i32 1, label %idx1
108  i32 2, label %idx2
109  i32 3, label %idx3
110  i32 4, label %idx4
111  i32 5, label %idx5
112  i32 6, label %idx6
113  i32 7, label %idx7
114  i32 8, label %idx8
115  i32 9, label %idx9
116  i32 10, label %idx10
117  i32 11, label %idx11
118  i32 12, label %idx12
119  i32 13, label %idx13
120  i32 14, label %idx14
121  i32 15, label %idx15
122  ]
123idx0:
124  %res0_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 0
125  %res0 = zext <16 x i1> %res0_i1 to <16 x i8>
126  ret <16 x i8> %res0
127idx1:
128  %res1_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 1
129  %res1 = zext <16 x i1> %res1_i1 to <16 x i8>
130  ret <16 x i8> %res1
131idx2:
132  %res2_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 2
133  %res2 = zext <16 x i1> %res2_i1 to <16 x i8>
134  ret <16 x i8> %res2
135idx3:
136  %res3_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 3
137  %res3 = zext <16 x i1> %res3_i1 to <16 x i8>
138  ret <16 x i8> %res3
139idx4:
140  %res4_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 4
141  %res4 = zext <16 x i1> %res4_i1 to <16 x i8>
142  ret <16 x i8> %res4
143idx5:
144  %res5_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 5
145  %res5 = zext <16 x i1> %res5_i1 to <16 x i8>
146  ret <16 x i8> %res5
147idx6:
148  %res6_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 6
149  %res6 = zext <16 x i1> %res6_i1 to <16 x i8>
150  ret <16 x i8> %res6
151idx7:
152  %res7_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 7
153  %res7 = zext <16 x i1> %res7_i1 to <16 x i8>
154  ret <16 x i8> %res7
155idx8:
156  %res8_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 8
157  %res8 = zext <16 x i1> %res8_i1 to <16 x i8>
158  ret <16 x i8> %res8
159idx9:
160  %res9_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 9
161  %res9 = zext <16 x i1> %res9_i1 to <16 x i8>
162  ret <16 x i8> %res9
163idx10:
164  %res10_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 10
165  %res10 = zext <16 x i1> %res10_i1 to <16 x i8>
166  ret <16 x i8> %res10
167idx11:
168  %res11_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 11
169  %res11 = zext <16 x i1> %res11_i1 to <16 x i8>
170  ret <16 x i8> %res11
171idx12:
172  %res12_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 12
173  %res12 = zext <16 x i1> %res12_i1 to <16 x i8>
174  ret <16 x i8> %res12
175idx13:
176  %res13_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 13
177  %res13 = zext <16 x i1> %res13_i1 to <16 x i8>
178  ret <16 x i8> %res13
179idx14:
180  %res14_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 14
181  %res14 = zext <16 x i1> %res14_i1 to <16 x i8>
182  ret <16 x i8> %res14
183idx15:
184  %res15_i1 = insertelement <16 x i1> %vec, i1 %elt, i32 15
185  %res15 = zext <16 x i1> %res15_i1 to <16 x i8>
186  ret <16 x i8> %res15
187abort:
188  unreachable
189}
190
191define <4 x i32> @insertelement_v4si32(<4 x i32> %vec, i64 %elt_arg, i32 %idx) {
192entry:
193  %elt = trunc i64 %elt_arg to i32
194  switch i32 %idx, label %abort [
195  i32 0, label %idx0
196  i32 1, label %idx1
197  i32 2, label %idx2
198  i32 3, label %idx3
199  ]
200idx0:
201  %res0 = insertelement <4 x i32> %vec, i32 %elt, i32 0
202  ret <4 x i32> %res0
203idx1:
204  %res1 = insertelement <4 x i32> %vec, i32 %elt, i32 1
205  ret <4 x i32> %res1
206idx2:
207  %res2 = insertelement <4 x i32> %vec, i32 %elt, i32 2
208  ret <4 x i32> %res2
209idx3:
210  %res3 = insertelement <4 x i32> %vec, i32 %elt, i32 3
211  ret <4 x i32> %res3
212abort:
213  unreachable
214}
215
216define <4 x i32> @insertelement_v4ui32(<4 x i32> %vec, i64 %elt_arg, i32 %idx) {
217entry:
218  %res = call <4 x i32> @insertelement_v4si32(<4 x i32> %vec, i64 %elt_arg, i32 %idx)
219  ret <4 x i32> %res
220}
221
222define <8 x i16> @insertelement_v8si16(<8 x i16> %vec, i64 %elt_arg, i32 %idx) {
223entry:
224  %elt = trunc i64 %elt_arg to i16
225  switch i32 %idx, label %abort [
226  i32 0, label %idx0
227  i32 1, label %idx1
228  i32 2, label %idx2
229  i32 3, label %idx3
230  i32 4, label %idx4
231  i32 5, label %idx5
232  i32 6, label %idx6
233  i32 7, label %idx7
234  ]
235idx0:
236  %res0 = insertelement <8 x i16> %vec, i16 %elt, i32 0
237  ret <8 x i16> %res0
238idx1:
239  %res1 = insertelement <8 x i16> %vec, i16 %elt, i32 1
240  ret <8 x i16> %res1
241idx2:
242  %res2 = insertelement <8 x i16> %vec, i16 %elt, i32 2
243  ret <8 x i16> %res2
244idx3:
245  %res3 = insertelement <8 x i16> %vec, i16 %elt, i32 3
246  ret <8 x i16> %res3
247idx4:
248  %res4 = insertelement <8 x i16> %vec, i16 %elt, i32 4
249  ret <8 x i16> %res4
250idx5:
251  %res5 = insertelement <8 x i16> %vec, i16 %elt, i32 5
252  ret <8 x i16> %res5
253idx6:
254  %res6 = insertelement <8 x i16> %vec, i16 %elt, i32 6
255  ret <8 x i16> %res6
256idx7:
257  %res7 = insertelement <8 x i16> %vec, i16 %elt, i32 7
258  ret <8 x i16> %res7
259abort:
260  unreachable
261}
262
263define <8 x i16> @insertelement_v8ui16(<8 x i16> %vec, i64 %elt_arg, i32 %idx) {
264entry:
265  %res = call <8 x i16> @insertelement_v8si16(<8 x i16> %vec, i64 %elt_arg, i32 %idx)
266  ret <8 x i16> %res
267}
268
269define <16 x i8> @insertelement_v16si8(<16 x i8> %vec, i64 %elt_arg, i32 %idx) {
270entry:
271  %elt = trunc i64 %elt_arg to i8
272  switch i32 %idx, label %abort [
273  i32 0, label %idx0
274  i32 1, label %idx1
275  i32 2, label %idx2
276  i32 3, label %idx3
277  i32 4, label %idx4
278  i32 5, label %idx5
279  i32 6, label %idx6
280  i32 7, label %idx7
281  i32 8, label %idx8
282  i32 9, label %idx9
283  i32 10, label %idx10
284  i32 11, label %idx11
285  i32 12, label %idx12
286  i32 13, label %idx13
287  i32 14, label %idx14
288  i32 15, label %idx15
289  ]
290idx0:
291  %res0 = insertelement <16 x i8> %vec, i8 %elt, i32 0
292  ret <16 x i8> %res0
293idx1:
294  %res1 = insertelement <16 x i8> %vec, i8 %elt, i32 1
295  ret <16 x i8> %res1
296idx2:
297  %res2 = insertelement <16 x i8> %vec, i8 %elt, i32 2
298  ret <16 x i8> %res2
299idx3:
300  %res3 = insertelement <16 x i8> %vec, i8 %elt, i32 3
301  ret <16 x i8> %res3
302idx4:
303  %res4 = insertelement <16 x i8> %vec, i8 %elt, i32 4
304  ret <16 x i8> %res4
305idx5:
306  %res5 = insertelement <16 x i8> %vec, i8 %elt, i32 5
307  ret <16 x i8> %res5
308idx6:
309  %res6 = insertelement <16 x i8> %vec, i8 %elt, i32 6
310  ret <16 x i8> %res6
311idx7:
312  %res7 = insertelement <16 x i8> %vec, i8 %elt, i32 7
313  ret <16 x i8> %res7
314idx8:
315  %res8 = insertelement <16 x i8> %vec, i8 %elt, i32 8
316  ret <16 x i8> %res8
317idx9:
318  %res9 = insertelement <16 x i8> %vec, i8 %elt, i32 9
319  ret <16 x i8> %res9
320idx10:
321  %res10 = insertelement <16 x i8> %vec, i8 %elt, i32 10
322  ret <16 x i8> %res10
323idx11:
324  %res11 = insertelement <16 x i8> %vec, i8 %elt, i32 11
325  ret <16 x i8> %res11
326idx12:
327  %res12 = insertelement <16 x i8> %vec, i8 %elt, i32 12
328  ret <16 x i8> %res12
329idx13:
330  %res13 = insertelement <16 x i8> %vec, i8 %elt, i32 13
331  ret <16 x i8> %res13
332idx14:
333  %res14 = insertelement <16 x i8> %vec, i8 %elt, i32 14
334  ret <16 x i8> %res14
335idx15:
336  %res15 = insertelement <16 x i8> %vec, i8 %elt, i32 15
337  ret <16 x i8> %res15
338abort:
339  unreachable
340}
341
342define <16 x i8> @insertelement_v16ui8(<16 x i8> %vec, i64 %elt_arg, i32 %idx) {
343entry:
344  %res = call <16 x i8> @insertelement_v16si8(<16 x i8> %vec, i64 %elt_arg, i32 %idx)
345  ret <16 x i8> %res
346}
347
348define float @extractelement_v4f32(<4 x float> %vec, i32 %idx) {
349  switch i32 %idx, label %abort [
350  i32 0, label %idx0
351  i32 1, label %idx1
352  i32 2, label %idx2
353  i32 3, label %idx3
354  ]
355idx0:
356  %res0 = extractelement <4 x float> %vec, i32 0
357  ret float %res0
358idx1:
359  %res1 = extractelement <4 x float> %vec, i32 1
360  ret float %res1
361idx2:
362  %res2 = extractelement <4 x float> %vec, i32 2
363  ret float %res2
364idx3:
365  %res3 = extractelement <4 x float> %vec, i32 3
366  ret float %res3
367abort:
368  unreachable
369}
370
371define i64 @extractelement_v4i1(<4 x i32> %arg_vec, i32 %idx) {
372  %vec = trunc <4 x i32> %arg_vec to <4 x i1>
373  switch i32 %idx, label %abort [
374  i32 0, label %idx0
375  i32 1, label %idx1
376  i32 2, label %idx2
377  i32 3, label %idx3
378  ]
379idx0:
380  %res0_i1 = extractelement <4 x i1> %vec, i32 0
381  %res0 = zext i1 %res0_i1 to i64
382  ret i64 %res0
383idx1:
384  %res1_i1 = extractelement <4 x i1> %vec, i32 1
385  %res1 = zext i1 %res1_i1 to i64
386  ret i64 %res1
387idx2:
388  %res2_i1 = extractelement <4 x i1> %vec, i32 2
389  %res2 = zext i1 %res2_i1 to i64
390  ret i64 %res2
391idx3:
392  %res3_i1 = extractelement <4 x i1> %vec, i32 3
393  %res3 = zext i1 %res3_i1 to i64
394  ret i64 %res3
395abort:
396  unreachable
397}
398
399define i64 @extractelement_v8i1(<8 x i16> %arg_vec, i32 %idx) {
400  %vec = trunc <8 x i16> %arg_vec to <8 x i1>
401  switch i32 %idx, label %abort [
402  i32 0, label %idx0
403  i32 1, label %idx1
404  i32 2, label %idx2
405  i32 3, label %idx3
406  i32 4, label %idx4
407  i32 5, label %idx5
408  i32 6, label %idx6
409  i32 7, label %idx7
410  ]
411idx0:
412  %res0_i1 = extractelement <8 x i1> %vec, i32 0
413  %res0 = zext i1 %res0_i1 to i64
414  ret i64 %res0
415idx1:
416  %res1_i1 = extractelement <8 x i1> %vec, i32 1
417  %res1 = zext i1 %res1_i1 to i64
418  ret i64 %res1
419idx2:
420  %res2_i1 = extractelement <8 x i1> %vec, i32 2
421  %res2 = zext i1 %res2_i1 to i64
422  ret i64 %res2
423idx3:
424  %res3_i1 = extractelement <8 x i1> %vec, i32 3
425  %res3 = zext i1 %res3_i1 to i64
426  ret i64 %res3
427idx4:
428  %res4_i1 = extractelement <8 x i1> %vec, i32 4
429  %res4 = zext i1 %res4_i1 to i64
430  ret i64 %res4
431idx5:
432  %res5_i1 = extractelement <8 x i1> %vec, i32 5
433  %res5 = zext i1 %res5_i1 to i64
434  ret i64 %res5
435idx6:
436  %res6_i1 = extractelement <8 x i1> %vec, i32 6
437  %res6 = zext i1 %res6_i1 to i64
438  ret i64 %res6
439idx7:
440  %res7_i1 = extractelement <8 x i1> %vec, i32 7
441  %res7 = zext i1 %res7_i1 to i64
442  ret i64 %res7
443abort:
444  unreachable
445}
446
447define i64 @extractelement_v16i1(<16 x i8> %arg_vec, i32 %idx) {
448  %vec = trunc <16 x i8> %arg_vec to <16 x i1>
449  switch i32 %idx, label %abort [
450  i32 0, label %idx0
451  i32 1, label %idx1
452  i32 2, label %idx2
453  i32 3, label %idx3
454  i32 4, label %idx4
455  i32 5, label %idx5
456  i32 6, label %idx6
457  i32 7, label %idx7
458  i32 8, label %idx8
459  i32 9, label %idx9
460  i32 10, label %idx10
461  i32 11, label %idx11
462  i32 12, label %idx12
463  i32 13, label %idx13
464  i32 14, label %idx14
465  i32 15, label %idx15
466  ]
467idx0:
468  %res0_i1 = extractelement <16 x i1> %vec, i32 0
469  %res0 = zext i1 %res0_i1 to i64
470  ret i64 %res0
471idx1:
472  %res1_i1 = extractelement <16 x i1> %vec, i32 1
473  %res1 = zext i1 %res1_i1 to i64
474  ret i64 %res1
475idx2:
476  %res2_i1 = extractelement <16 x i1> %vec, i32 2
477  %res2 = zext i1 %res2_i1 to i64
478  ret i64 %res2
479idx3:
480  %res3_i1 = extractelement <16 x i1> %vec, i32 3
481  %res3 = zext i1 %res3_i1 to i64
482  ret i64 %res3
483idx4:
484  %res4_i1 = extractelement <16 x i1> %vec, i32 4
485  %res4 = zext i1 %res4_i1 to i64
486  ret i64 %res4
487idx5:
488  %res5_i1 = extractelement <16 x i1> %vec, i32 5
489  %res5 = zext i1 %res5_i1 to i64
490  ret i64 %res5
491idx6:
492  %res6_i1 = extractelement <16 x i1> %vec, i32 6
493  %res6 = zext i1 %res6_i1 to i64
494  ret i64 %res6
495idx7:
496  %res7_i1 = extractelement <16 x i1> %vec, i32 7
497  %res7 = zext i1 %res7_i1 to i64
498  ret i64 %res7
499idx8:
500  %res8_i1 = extractelement <16 x i1> %vec, i32 8
501  %res8 = zext i1 %res8_i1 to i64
502  ret i64 %res8
503idx9:
504  %res9_i1 = extractelement <16 x i1> %vec, i32 9
505  %res9 = zext i1 %res9_i1 to i64
506  ret i64 %res9
507idx10:
508  %res10_i1 = extractelement <16 x i1> %vec, i32 10
509  %res10 = zext i1 %res10_i1 to i64
510  ret i64 %res10
511idx11:
512  %res11_i1 = extractelement <16 x i1> %vec, i32 11
513  %res11 = zext i1 %res11_i1 to i64
514  ret i64 %res11
515idx12:
516  %res12_i1 = extractelement <16 x i1> %vec, i32 12
517  %res12 = zext i1 %res12_i1 to i64
518  ret i64 %res12
519idx13:
520  %res13_i1 = extractelement <16 x i1> %vec, i32 13
521  %res13 = zext i1 %res13_i1 to i64
522  ret i64 %res13
523idx14:
524  %res14_i1 = extractelement <16 x i1> %vec, i32 14
525  %res14 = zext i1 %res14_i1 to i64
526  ret i64 %res14
527idx15:
528  %res15_i1 = extractelement <16 x i1> %vec, i32 15
529  %res15 = zext i1 %res15_i1 to i64
530  ret i64 %res15
531abort:
532  unreachable
533}
534
535define i64 @extractelement_v4si32(<4 x i32> %vec, i32 %idx) {
536entry:
537  switch i32 %idx, label %abort [
538  i32 0, label %idx0
539  i32 1, label %idx1
540  i32 2, label %idx2
541  i32 3, label %idx3
542  ]
543idx0:
544  %res0_i32 = extractelement <4 x i32> %vec, i32 0
545  %res0 = zext i32 %res0_i32 to i64
546  ret i64 %res0
547idx1:
548  %res1_i32 = extractelement <4 x i32> %vec, i32 1
549  %res1 = zext i32 %res1_i32 to i64
550  ret i64 %res1
551idx2:
552  %res2_i32 = extractelement <4 x i32> %vec, i32 2
553  %res2 = zext i32 %res2_i32 to i64
554  ret i64 %res2
555idx3:
556  %res3_i32 = extractelement <4 x i32> %vec, i32 3
557  %res3 = zext i32 %res3_i32 to i64
558  ret i64 %res3
559abort:
560  unreachable
561}
562
563define i64 @extractelement_v4ui32(<4 x i32> %vec, i32 %idx) {
564entry:
565  %res = call i64 @extractelement_v4si32(<4 x i32> %vec, i32 %idx)
566  ret i64 %res
567}
568
569define i64 @extractelement_v8si16(<8 x i16> %vec, i32 %idx) {
570entry:
571  switch i32 %idx, label %abort [
572  i32 0, label %idx0
573  i32 1, label %idx1
574  i32 2, label %idx2
575  i32 3, label %idx3
576  i32 4, label %idx4
577  i32 5, label %idx5
578  i32 6, label %idx6
579  i32 7, label %idx7
580  ]
581idx0:
582  %res0_i16 = extractelement <8 x i16> %vec, i32 0
583  %res0 = zext i16 %res0_i16 to i64
584  ret i64 %res0
585idx1:
586  %res1_i16 = extractelement <8 x i16> %vec, i32 1
587  %res1 = zext i16 %res1_i16 to i64
588  ret i64 %res1
589idx2:
590  %res2_i16 = extractelement <8 x i16> %vec, i32 2
591  %res2 = zext i16 %res2_i16 to i64
592  ret i64 %res2
593idx3:
594  %res3_i16 = extractelement <8 x i16> %vec, i32 3
595  %res3 = zext i16 %res3_i16 to i64
596  ret i64 %res3
597idx4:
598  %res4_i16 = extractelement <8 x i16> %vec, i32 4
599  %res4 = zext i16 %res4_i16 to i64
600  ret i64 %res4
601idx5:
602  %res5_i16 = extractelement <8 x i16> %vec, i32 5
603  %res5 = zext i16 %res5_i16 to i64
604  ret i64 %res5
605idx6:
606  %res6_i16 = extractelement <8 x i16> %vec, i32 6
607  %res6 = zext i16 %res6_i16 to i64
608  ret i64 %res6
609idx7:
610  %res7_i16 = extractelement <8 x i16> %vec, i32 7
611  %res7 = zext i16 %res7_i16 to i64
612  ret i64 %res7
613abort:
614  unreachable
615}
616
617define i64 @extractelement_v8ui16(<8 x i16> %vec, i32 %idx) {
618entry:
619  %res = call i64 @extractelement_v8si16(<8 x i16> %vec, i32 %idx)
620  ret i64 %res
621}
622
623define i64 @extractelement_v16si8(<16 x i8> %vec, i32 %idx) {
624entry:
625  switch i32 %idx, label %abort [
626  i32 0, label %idx0
627  i32 1, label %idx1
628  i32 2, label %idx2
629  i32 3, label %idx3
630  i32 4, label %idx4
631  i32 5, label %idx5
632  i32 6, label %idx6
633  i32 7, label %idx7
634  i32 8, label %idx8
635  i32 9, label %idx9
636  i32 10, label %idx10
637  i32 11, label %idx11
638  i32 12, label %idx12
639  i32 13, label %idx13
640  i32 14, label %idx14
641  i32 15, label %idx15
642  ]
643idx0:
644  %res0_i8 = extractelement <16 x i8> %vec, i32 0
645  %res0 = zext i8 %res0_i8 to i64
646  ret i64 %res0
647idx1:
648  %res1_i8 = extractelement <16 x i8> %vec, i32 1
649  %res1 = zext i8 %res1_i8 to i64
650  ret i64 %res1
651idx2:
652  %res2_i8 = extractelement <16 x i8> %vec, i32 2
653  %res2 = zext i8 %res2_i8 to i64
654  ret i64 %res2
655idx3:
656  %res3_i8 = extractelement <16 x i8> %vec, i32 3
657  %res3 = zext i8 %res3_i8 to i64
658  ret i64 %res3
659idx4:
660  %res4_i8 = extractelement <16 x i8> %vec, i32 4
661  %res4 = zext i8 %res4_i8 to i64
662  ret i64 %res4
663idx5:
664  %res5_i8 = extractelement <16 x i8> %vec, i32 5
665  %res5 = zext i8 %res5_i8 to i64
666  ret i64 %res5
667idx6:
668  %res6_i8 = extractelement <16 x i8> %vec, i32 6
669  %res6 = zext i8 %res6_i8 to i64
670  ret i64 %res6
671idx7:
672  %res7_i8 = extractelement <16 x i8> %vec, i32 7
673  %res7 = zext i8 %res7_i8 to i64
674  ret i64 %res7
675idx8:
676  %res8_i8 = extractelement <16 x i8> %vec, i32 8
677  %res8 = zext i8 %res8_i8 to i64
678  ret i64 %res8
679idx9:
680  %res9_i8 = extractelement <16 x i8> %vec, i32 9
681  %res9 = zext i8 %res9_i8 to i64
682  ret i64 %res9
683idx10:
684  %res10_i8 = extractelement <16 x i8> %vec, i32 10
685  %res10 = zext i8 %res10_i8 to i64
686  ret i64 %res10
687idx11:
688  %res11_i8 = extractelement <16 x i8> %vec, i32 11
689  %res11 = zext i8 %res11_i8 to i64
690  ret i64 %res11
691idx12:
692  %res12_i8 = extractelement <16 x i8> %vec, i32 12
693  %res12 = zext i8 %res12_i8 to i64
694  ret i64 %res12
695idx13:
696  %res13_i8 = extractelement <16 x i8> %vec, i32 13
697  %res13 = zext i8 %res13_i8 to i64
698  ret i64 %res13
699idx14:
700  %res14_i8 = extractelement <16 x i8> %vec, i32 14
701  %res14 = zext i8 %res14_i8 to i64
702  ret i64 %res14
703idx15:
704  %res15_i8 = extractelement <16 x i8> %vec, i32 15
705  %res15 = zext i8 %res15_i8 to i64
706  ret i64 %res15
707abort:
708  unreachable
709}
710
711define i64 @extractelement_v16ui8(<16 x i8> %vec, i32 %idx) {
712entry:
713  %res = call i64 @extractelement_v16si8(<16 x i8> %vec, i32 %idx)
714  ret i64 %res
715}
716