1; Show that we know how to translate veor vector instructions. 2 3; REQUIRES: allow_dump 4 5; Compile using standalone assembler. 6; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \ 7; RUN: | FileCheck %s --check-prefix=ASM 8 9; Show bytes in assembled standalone code. 10; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \ 11; RUN: --args -O2 \ 12; RUN: | FileCheck %s --check-prefix=DIS 13 14; Compile using integrated assembler. 15; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \ 16; RUN: | FileCheck %s --check-prefix=IASM 17 18; Show bytes in assembled integrated code. 19; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \ 20; RUN: --args -O2 \ 21; RUN: | FileCheck %s --check-prefix=DIS 22 23define internal <4 x i32> @testVxor4i32(<4 x i32> %v1, <4 x i32> %v2) { 24; ASM-LABEL: testVxor4i32: 25; DIS-LABEL: 00000000 <testVxor4i32>: 26; IASM-LABEL: testVxor4i32: 27 28entry: 29 %res = xor <4 x i32> %v1, %v2 30 31; ASM: veor.i32 q0, q0, q1 32; DIS: 0: f3000152 33; IASM-NOT: veor.i32 34 35 ret <4 x i32> %res 36} 37 38define internal <8 x i16> @testVxor8i16(<8 x i16> %v1, <8 x i16> %v2) { 39; ASM-LABEL: testVxor8i16: 40; DIS-LABEL: 00000010 <testVxor8i16>: 41; IASM-LABEL: testVxor8i16: 42 43entry: 44 %res = xor <8 x i16> %v1, %v2 45 46; ASM: veor.i16 q0, q0, q1 47; DIS: 10: f3000152 48; IASM-NOT: veor.i16 49 50 ret <8 x i16> %res 51} 52 53define internal <16 x i8> @testVxor16i8(<16 x i8> %v1, <16 x i8> %v2) { 54; ASM-LABEL: testVxor16i8: 55; DIS-LABEL: 00000020 <testVxor16i8>: 56; IASM-LABEL: testVxor16i8: 57 58entry: 59 %res = xor <16 x i8> %v1, %v2 60 61; ASM: veor.i8 q0, q0, q1 62; DIS: 20: f3000152 63; IASM-NOT: veor.i8 64 65 ret <16 x i8> %res 66} 67 68;; 69;; The following tests make sure logical xor works on predicate vectors. 70;; 71 72define internal <4 x i1> @testVxor4i1(<4 x i1> %v1, <4 x i1> %v2) { 73; ASM-LABEL: testVxor4i1: 74; DIS-LABEL: 00000030 <testVxor4i1>: 75; IASM-LABEL: testVxor4i1: 76 77entry: 78 %res = xor <4 x i1> %v1, %v2 79 80; ASM: veor.i32 q0, q0, q1 81; DIS: 30: f3000152 82; IASM-NOT: veor.i32 83 84 ret <4 x i1> %res 85} 86 87define internal <8 x i1> @testVxor8i1(<8 x i1> %v1, <8 x i1> %v2) { 88; ASM-LABEL: testVxor8i1: 89; DIS-LABEL: 00000040 <testVxor8i1>: 90; IASM-LABEL: testVxor8i1: 91 92entry: 93 %res = xor <8 x i1> %v1, %v2 94 95; ASM: veor.i16 q0, q0, q1 96; DIS: 40: f3000152 97; IASM-NOT: veor.i16 98 99 ret <8 x i1> %res 100} 101 102define internal <16 x i1> @testVxor16i1(<16 x i1> %v1, <16 x i1> %v2) { 103; ASM-LABEL: testVxor16i1: 104; DIS-LABEL: 00000050 <testVxor16i1>: 105; IASM-LABEL: testVxor16i1: 106 107entry: 108 %res = xor <16 x i1> %v1, %v2 109 110; ASM: veor.i8 q0, q0, q1 111; DIS: 50: f3000152 112; IASM-NOT: veor.i8 113 114 ret <16 x i1> %res 115} 116