1; This tries to be a comprehensive test of f32 and f64 call/return ops. 2; The CHECK lines are only checking for basic instruction patterns 3; that should be present regardless of the optimization level, so 4; there are no special OPTM1 match lines. 5 6; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 7; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \ 8; RUN: | %if --need=target_X8632 --command FileCheck %s 9; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ 10; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \ 11; RUN: | %if --need=target_X8632 --command FileCheck %s 12 13; RUN: %if --need=target_MIPS32 --need=allow_dump \ 14; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \ 15; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \ 16; RUN: | %if --need=target_MIPS32 --need=allow_dump \ 17; RUN: --command FileCheck --check-prefix MIPS32 %s 18 19; Can't test on ARM yet. Need to use several vpush {contiguous FP regs}, 20; instead of push {any GPR list}. 21 22define internal i32 @doubleArgs(double %a, i32 %b, double %c) { 23entry: 24 ret i32 %b 25} 26; CHECK-LABEL: doubleArgs 27; CHECK: mov eax,DWORD PTR [esp+0xc] 28; CHECK-NEXT: ret 29; ARM32-LABEL: doubleArgs 30; MIPS32-LABEL: doubleArgs 31; MIPS32: move v0,a2 32; MIPS32: jr ra 33 34define internal i32 @floatArgs(float %a, i32 %b, float %c) { 35entry: 36 ret i32 %b 37} 38; CHECK-LABEL: floatArgs 39; CHECK: mov eax,DWORD PTR [esp+0x8] 40; CHECK-NEXT: ret 41; MIPS32-LABEL: floatArgs 42; MIPS32: move v0,a1 43; MIPS32: jr ra 44 45define internal i32 @passFpArgs(float %a, double %b, float %c, double %d, float %e, double %f) { 46entry: 47 %call = call i32 @ignoreFpArgsNoInline(float %a, i32 123, double %b) 48 %call1 = call i32 @ignoreFpArgsNoInline(float %c, i32 123, double %d) 49 %call2 = call i32 @ignoreFpArgsNoInline(float %e, i32 123, double %f) 50 %add = add i32 %call1, %call 51 %add3 = add i32 %add, %call2 52 ret i32 %add3 53} 54; CHECK-LABEL: passFpArgs 55; CHECK: mov DWORD PTR [esp+0x4],0x7b 56; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline 57; CHECK: mov DWORD PTR [esp+0x4],0x7b 58; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline 59; CHECK: mov DWORD PTR [esp+0x4],0x7b 60; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline 61; MIPS32-LABEL: passFpArgs 62; MIPS32: mfc1 a2,$f{{[0-9]+}} 63; MIPS32: mfc1 a3,$f{{[0-9]+}} 64; MIPS32: li a1,123 65; MIPS32: jal {{.*}} ignoreFpArgsNoInline 66; MIPS32: mfc1 a2,$f{{[0-9]+}} 67; MIPS32: mfc1 a3,$f{{[0-9]+}} 68; MIPS32: li a1,123 69; MIPS32: jal {{.*}} ignoreFpArgsNoInline 70; MIPS32: mfc1 a2,$f{{[0-9]+}} 71; MIPS32: mfc1 a3,$f{{[0-9]+}} 72; MIPS32: li a1,123 73; MIPS32: jal {{.*}} ignoreFpArgsNoInline 74 75declare i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z) 76 77define internal i32 @passFpConstArg(float %a, double %b) { 78entry: 79 %call = call i32 @ignoreFpArgsNoInline(float %a, i32 123, double 2.340000e+00) 80 ret i32 %call 81} 82; CHECK-LABEL: passFpConstArg 83; CHECK: mov DWORD PTR [esp+0x4],0x7b 84; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline 85; MIPS32-LABEL: passFpConstArg 86; MIPS32: mfc1 a2,$f{{[0-9]+}} 87; MIPS32: mfc1 a3,$f{{[0-9]+}} 88; MIPS32: li a1,123 89; MIPS32: jal {{.*}} ignoreFpArgsNoInline 90 91define internal i32 @passFp32ConstArg(float %a) { 92entry: 93 %call = call i32 @ignoreFp32ArgsNoInline(float %a, i32 123, float 2.0) 94 ret i32 %call 95} 96; CHECK-LABEL: passFp32ConstArg 97; CHECK: mov DWORD PTR [esp+0x4],0x7b 98; CHECK: movss DWORD PTR [esp+0x8] 99; CHECK: call {{.*}} R_{{.*}} ignoreFp32ArgsNoInline 100; MIPS32-LABEL: passFp32ConstArg 101; MIPS32: mfc1 a2,$f0 102; MIPS32: li a1,123 103; MIPS32: jal {{.*}} ignoreFp32ArgsNoInline 104 105declare i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z) 106 107define internal float @returnFloatArg(float %a) { 108entry: 109 ret float %a 110} 111; CHECK-LABEL: returnFloatArg 112; CHECK: fld DWORD PTR [esp 113; MIPS32-LABEL: returnFloatArg 114; MIPS32: mov.s $f0,$f12 115; MIPS32: jr ra 116 117define internal double @returnDoubleArg(double %a) { 118entry: 119 ret double %a 120} 121; CHECK-LABEL: returnDoubleArg 122; CHECK: fld QWORD PTR [esp 123; MIPS32-LABEL: returnDoubleArg 124; MIPS32: mov.d $f0,$f12 125; MIPS32: jr ra 126 127define internal float @returnFloatConst() { 128entry: 129 ret float 0x3FF3AE1480000000 130} 131; CHECK-LABEL: returnFloatConst 132; CHECK: fld 133; MIPS32-LABEL: returnFloatConst 134; MIPS32: lui v0,0x0 {{.*}} .L$float$3f9d70a4 135; MIPS32: lwc1 $f0,0(v0) {{.*}} .L$float$3f9d70a4 136; MIPS32: jr ra 137 138define internal double @returnDoubleConst() { 139entry: 140 ret double 1.230000e+00 141} 142; CHECK-LABEL: returnDoubleConst 143; CHECK: fld 144; MIPS32-LABEL: returnDoubleConst 145; MIPS32: lui v0,0x0 {{.*}} .L$double$3ff3ae147ae147ae 146; MIPS32: ldc1 $f0,0(v0) {{.*}} .L$double$3ff3ae147ae147ae 147; MIPS32: jr ra 148