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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2014, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6 
7 #include <asm/io.h>
8 #include <asm/arch/stv0991_creg.h>
9 #include <asm/arch/stv0991_periph.h>
10 #include <asm/arch/hardware.h>
11 
12 static struct stv0991_creg *const stv0991_creg = \
13 			(struct stv0991_creg *)CREG_BASE_ADDR;
14 
stv0991_pinmux_config(int peripheral)15 int stv0991_pinmux_config(int peripheral)
16 {
17 	switch (peripheral) {
18 	case UART_GPIOC_30_31:
19 		/* SSDA/SSCL pad muxing to UART Rx/Dx */
20 		writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
21 				CFG_GPIOC_31_UART_RX,
22 				&stv0991_creg->mux12);
23 		writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
24 				CFG_GPIOC_30_UART_TX,
25 				&stv0991_creg->mux12);
26 		/* SSDA/SSCL pad config to push pull*/
27 		writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
28 				CFG_GPIOC_31_MODE_PP,
29 				&stv0991_creg->cfg_pad6);
30 		writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
31 				CFG_GPIOC_30_MODE_HIGH,
32 				&stv0991_creg->cfg_pad6);
33 		break;
34 	case UART_GPIOB_16_17:
35 		/* ethernet rx_6/7 to UART Rx/Dx */
36 		writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
37 				CFG_GPIOB_17_UART_RX,
38 				&stv0991_creg->mux7);
39 		writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
40 				CFG_GPIOB_16_UART_TX,
41 				&stv0991_creg->mux7);
42 		break;
43 	case ETH_GPIOB_10_31_C_0_4:
44 		writel(readl(&stv0991_creg->mux6) & 0x000000FF,
45 				&stv0991_creg->mux6);
46 		writel(0x00000000, &stv0991_creg->mux7);
47 		writel(0x00000000, &stv0991_creg->mux8);
48 		writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
49 				&stv0991_creg->mux9);
50 		/* Ethernet Voltage configuration to 1.8V*/
51 		writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
52 				ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
53 		writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
54 				ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
55 
56 		break;
57 	case QSPI_CS_CLK_PAD:
58 		writel((readl(&stv0991_creg->mux13) & FLASH_CS_NC_MASK) |
59 				CFG_FLASH_CS_NC, &stv0991_creg->mux13);
60 		writel((readl(&stv0991_creg->mux13) & FLASH_CLK_MASK) |
61 				CFG_FLASH_CLK, &stv0991_creg->mux13);
62 	default:
63 		break;
64 	}
65 	return 0;
66 }
67