1# 2# Copyright 2014-2015 Freescale Semiconductor 3# 4# SPDX-License-Identifier: GPL-2.0+ 5# 6 7Freescale LayerScape with Chassis Generation 3 8 9This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, 10for example LS2080A. 11 12DDR Layout 13============ 14Entire DDR region splits into two regions. 15 - Region 1 is at address 0x8000_0000 to 0xffff_ffff. 16 - Region 2 is at 0x80_8000_0000 to the top of total memory, 17 for example 16GB, 0x83_ffff_ffff. 18 19All DDR memory is marked as cache-enabled. 20 21When MC and Debug server is enabled, they carve 512MB away from the high 22end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB 23with MC and Debug server enabled. Linux only sees 15.5GB. 24 25The reserved 512MB layout looks like 26 27 +---------------+ <-- top/end of memory 28 | 256MB | debug server 29 +---------------+ 30 | 256MB | MC 31 +---------------+ 32 | ... | 33 34MC requires the memory to be aligned with 512MB, so even debug server is 35not enabled, 512MB is reserved, not 256MB. 36 37Flash Layout 38============ 39 40(1) A typical layout of various images (including Linux and other firmware images) 41 is shown below considering a 32MB NOR flash device present on most 42 pre-silicon platforms (simulator and emulator): 43 44 ------------------------- 45 | FIT Image | 46 | (linux + DTB + RFS) | 47 ------------------------- ----> 0x0120_0000 48 | Debug Server FW | 49 ------------------------- ----> 0x00C0_0000 50 | AIOP FW | 51 ------------------------- ----> 0x0070_0000 52 | MC FW | 53 ------------------------- ----> 0x006C_0000 54 | MC DPL Blob | 55 ------------------------- ----> 0x0020_0000 56 | BootLoader + Env| 57 ------------------------- ----> 0x0000_1000 58 | PBI | 59 ------------------------- ----> 0x0000_0080 60 | RCW | 61 ------------------------- ----> 0x0000_0000 62 63 32-MB NOR flash layout for pre-silicon platforms (simulator and emulator) 64 65(2) A typical layout of various images (including Linux and other firmware images) 66 is shown below considering a 128MB NOR flash device present on QDS and RDB 67 boards: 68 ----------------------------------------- ----> 0x5_8800_0000 --- 69 | .. Unused .. (7M) | | 70 ----------------------------------------- ----> 0x5_8790_0000 | 71 | FIT Image (linux + DTB + RFS) (40M) | | 72 ----------------------------------------- ----> 0x5_8510_0000 | 73 | PHY firmware (2M) | | 74 ----------------------------------------- ----> 0x5_84F0_0000 | 64K 75 | Debug Server FW (2M) | | Alt 76 ----------------------------------------- ----> 0x5_84D0_0000 | Bank 77 | AIOP FW (4M) | | 78 ----------------------------------------- ----> 0x5_8490_0000 (vbank4) 79 | MC DPC Blob (1M) | | 80 ----------------------------------------- ----> 0x5_8480_0000 | 81 | MC DPL Blob (1M) | | 82 ----------------------------------------- ----> 0x5_8470_0000 | 83 | MC FW (4M) | | 84 ----------------------------------------- ----> 0x5_8430_0000 | 85 | BootLoader Environment (1M) | | 86 ----------------------------------------- ----> 0x5_8420_0000 | 87 | BootLoader (1M) | | 88 ----------------------------------------- ----> 0x5_8410_0000 | 89 | RCW and PBI (1M) | | 90 ----------------------------------------- ----> 0x5_8400_0000 --- 91 | .. Unused .. (7M) | | 92 ----------------------------------------- ----> 0x5_8390_0000 | 93 | FIT Image (linux + DTB + RFS) (40M) | | 94 ----------------------------------------- ----> 0x5_8110_0000 | 95 | PHY firmware (2M) | | 96 ----------------------------------------- ----> 0x5_80F0_0000 | 64K 97 | Debug Server FW (2M) | | Bank 98 ----------------------------------------- ----> 0x5_80D0_0000 | 99 | AIOP FW (4M) | | 100 ----------------------------------------- ----> 0x5_8090_0000 (vbank0) 101 | MC DPC Blob (1M) | | 102 ----------------------------------------- ----> 0x5_8080_0000 | 103 | MC DPL Blob (1M) | | 104 ----------------------------------------- ----> 0x5_8070_0000 | 105 | MC FW (4M) | | 106 ----------------------------------------- ----> 0x5_8030_0000 | 107 | BootLoader Environment (1M) | | 108 ----------------------------------------- ----> 0x5_8020_0000 | 109 | BootLoader (1M) | | 110 ----------------------------------------- ----> 0x5_8010_0000 | 111 | RCW and PBI (1M) | | 112 ----------------------------------------- ----> 0x5_8000_0000 --- 113 114 128-MB NOR flash layout for QDS and RDB boards 115 116Environment Variables 117===================== 118mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined 119 the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed. 120 121mcmemsize: MC DRAM block size in hex. If this variable is not defined, the value 122 CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed. 123 124mcinitcmd: This environment variable is defined to initiate MC and DPL deployment 125 from the location where it is stored(NOR, NAND, SD, SATA, USB)during 126 u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR 127 will be null and MC will not be booted and DPL will not be applied 128 during U-boot booting.However the MC, DPC and DPL can be applied from 129 console independently. 130 The variable needs to be set from the console once and then on 131 rebooting the parameters set in the variable will automatically be 132 executed. The commmand is demostrated taking an example of mc boot 133 using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash: 134 135 cp.b 0xa0000000 0x580300000 $filesize 136 cp.b 0x80000000 0x580800000 $filesize 137 cp.b 0x90000000 0x580700000 $filesize 138 139 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000' 140 141 If only linux is to be booted then the mcinitcmd environment should be set as 142 143 setenv mcinitcmd 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 144 145 Here the addresses 0xa0000000, 0x80000000, 0x80000000 are of DDR to where 146 MC binary, DPC binary and DPL binary are stored and 0x580300000, 0x580800000 147 and 0x580700000 are addresses in NOR where these are copied. It is to be 148 noted that these addresses in 'fsl_mc start mc 0x580300000 0x580800000;fsl_mc apply DPL 0x580700000' 149 can be replaced with the addresses of DDR to 150 which these will be copied in case of these binaries being stored in other 151 devices like SATA, USB, NAND, SD etc. 152 153Booting from NAND 154------------------- 155Booting from NAND requires two images, RCW and u-boot-with-spl.bin. 156The difference between NAND boot RCW image and NOR boot image is the PBI 157command sequence. Below is one example for PBI commands for LS2085AQDS which 158uses NAND device with 2KB/page, block size 128KB. 159 1601) CCSR 4-byte write to 0x00e00404, data=0x00000000 1612) CCSR 4-byte write to 0x00e00400, data=0x1800a000 162The above two commands set bootloc register to 0x00000000_1800a000 where 163the u-boot code will be running in OCRAM. 164 1653) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000, 166BLOCK_SIZE=0x00014000 167This command copies u-boot image from NAND device into OCRAM. The values need 168to adjust accordingly. 169 170SRC should match the cfg_rcw_src, the reset config pins. It depends 171 on the NAND device. See reference manual for cfg_rcw_src. 172SRC_ADDR is the offset of u-boot-with-spl.bin image in NAND device. In 173 the example above, 128KB. For easy maintenance, we put it at 174 the beginning of next block from RCW. 175DEST_ADDR is fixed at 0x1800a000, matching bootloc set above. 176BLOCK_SIZE is the size to be copied by PBI. 177 178RCW image should be written to the beginning of NAND device. Example of using 179u-boot command 180 181nand write <rcw image in memory> 0 <size of rcw image> 182 183To form the NAND image, build u-boot with NAND config, for example, 184ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin. 185The u-boot image should be written to match SRC_ADDR, in above example 0x20000. 186 187nand write <u-boot image in memory> 200000 <size of u-boot image> 188 189With these two images in NAND device, the board can boot from NAND. 190 191Another example for LS2085ARDB boards, 192 1931) CCSR 4-byte write to 0x00e00404, data=0x00000000 1942) CCSR 4-byte write to 0x00e00400, data=0x1800a000 1953) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000, 196BLOCK_SIZE=0x00014000 197 198nand write <rcw image in memory> 0 <size of rcw image> 199nand write <u-boot image in memory> 80000 <size of u-boot image> 200 201Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image 202to match board NAND device with 4KB/page, block size 512KB. 203 204Note, LS2088A and LS1088A don't support booting from NAND. 205 206Booting from SD/eMMC 207------------------- 208Booting from SD/eMMC requires two images, RCW and u-boot-with-spl.bin. 209The difference between SD boot RCW image and QSPI-NOR boot image is the 210PBI command sequence. Below is one example for PBI commands for RDB 211and QDS which uses SD device with block size 512. Block location can be 212calculated by dividing offset with block size. 213 2141) Block Copy: SRC=0x0040, SRC_ADDR=0x00100000, DEST_ADDR=0x1800a000, 215BLOCK_SIZE=0x00016000 216 217This command copies u-boot image from SD device into OCRAM. The values 218need to adjust accordingly for SD/eMMC 219 220SRC should match the cfg_rcw_src, the reset config pins. 221 The value for source(SRC) can be 0x0040 or 0x0041 222 depending upon SD or eMMC. 223SRC_ADDR is the offset of u-boot-with-spl.bin image in SD device. 224 In the example above, 1MB. This is same as QSPI-NOR. 225DEST_ADDR is configured at 0x1800a000, matching bootloc set above. 226BLOCK_SIZE is the size to be copied by PBI. 227 2282) CCSR 4-byte write to 0x01e00404, data=0x00000000 2293) CCSR 4-byte write to 0x01e00400, data=0x1800a000 230The above two commands set bootloc register to 0x00000000_1800a000 where 231the u-boot code will be running in OCRAM. 232 233 234RCW image should be written at 8th block of device(SD/eMMC). Example of 235using u-boot command 236 237mmc erase 0x8 0x10 238mmc write <rcw image in memory> 0x8 <size of rcw in block count typical value=10> 239 240To form the SD-Boot image, build u-boot with SD config, for example, 241ls1088ardb_sdcard_qspi_defconfig. The image needed is u-boot-with-spl.bin. 242The u-boot image should be written to match SRC_ADDR, in above example 243offset 0x100000 in other work it means block location 0x800 244 245mmc erase 0x800 0x1800 246mmc write <u-boot image in memory> 0x800 <size of u-boot image in block count> 247 248With these two images in SD/eMMC device, the board can boot from SD/eMMC. 249 250MMU Translation Tables 251====================== 252 253(1) Early MMU Tables: 254 255 Level 0 Level 1 Level 2 256------------------ ------------------ ------------------ 257| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 258------------------ ------------------ ------------------ 259| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 260------------------ | ------------------ ------------------ 261| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 262------------------ | ------------------ ------------------ 263 | | 0x00_c000_0000 | | 0x00_0060_0000 | 264 | ------------------ ------------------ 265 | | 0x01_0000_0000 | | 0x00_0080_0000 | 266 | ------------------ ------------------ 267 | ... ... 268 | ------------------ 269 | | 0x05_8000_0000 | --| 270 | ------------------ | 271 | | 0x05_c000_0000 | | 272 | ------------------ | 273 | ... | 274 | ------------------ | ------------------ 275 |--> | 0x80_0000_0000 | |-> | 0x00_3000_0000 | 276 ------------------ ------------------ 277 | 0x80_4000_0000 | | 0x00_3020_0000 | 278 ------------------ ------------------ 279 | 0x80_8000_0000 | | 0x00_3040_0000 | 280 ------------------ ------------------ 281 | 0x80_c000_0000 | | 0x00_3060_0000 | 282 ------------------ ------------------ 283 | 0x81_0000_0000 | | 0x00_3080_0000 | 284 ------------------ ------------------ 285 ... ... 286 287(2) Final MMU Tables: 288 289 Level 0 Level 1 Level 2 290------------------ ------------------ ------------------ 291| 0x00_0000_0000 | -----> | 0x00_0000_0000 | -----> | 0x00_0000_0000 | 292------------------ ------------------ ------------------ 293| 0x80_0000_0000 | --| | 0x00_4000_0000 | | 0x00_0020_0000 | 294------------------ | ------------------ ------------------ 295| invalid | | | 0x00_8000_0000 | | 0x00_0040_0000 | 296------------------ | ------------------ ------------------ 297 | | 0x00_c000_0000 | | 0x00_0060_0000 | 298 | ------------------ ------------------ 299 | | 0x01_0000_0000 | | 0x00_0080_0000 | 300 | ------------------ ------------------ 301 | ... ... 302 | ------------------ 303 | | 0x08_0000_0000 | --| 304 | ------------------ | 305 | | 0x08_4000_0000 | | 306 | ------------------ | 307 | ... | 308 | ------------------ | ------------------ 309 |--> | 0x80_0000_0000 | |--> | 0x08_0000_0000 | 310 ------------------ ------------------ 311 | 0x80_4000_0000 | | 0x08_0020_0000 | 312 ------------------ ------------------ 313 | 0x80_8000_0000 | | 0x08_0040_0000 | 314 ------------------ ------------------ 315 | 0x80_c000_0000 | | 0x08_0060_0000 | 316 ------------------ ------------------ 317 | 0x81_0000_0000 | | 0x08_0080_0000 | 318 ------------------ ------------------ 319 ... ... 320 321 322DPAA2 commands to manage Management Complex (MC) 323------------------------------------------------ 324DPAA2 commands has been introduced to manage Management Complex 325(MC). These commands are used to start mc, aiop and apply DPL 326from u-boot command prompt. 327 328Please note Management complex Firmware(MC), DPL and DPC are no 329more deployed during u-boot boot-sequence. 330 331Commands: 332a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 333b) fsl_mc apply DPL <DPL_addr> - Apply DPL file 334c) fsl_mc start aiop <FW_addr> - Start AIOP 335 336How to use commands :- 3371. Command sequence for u-boot ethernet: 338 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 339 b) DPMAC net-devices are now available for use 340 341 Example- 342 Assumption: MC firmware, DPL and DPC dtb is already programmed 343 on NOR flash. 344 345 => fsl_mc start mc 580300000 580800000 346 => setenv ethact DPMAC1@xgmii 347 => ping $serverip 348 3492. Command sequence for Linux boot: 350 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 351 b) fsl_mc apply DPL <DPL_addr> - Apply DPL file 352 c) No DPMAC net-devices are available for use in u-boot 353 d) boot Linux 354 355 Example- 356 Assumption: MC firmware, DPL and DPC dtb is already programmed 357 on NOR flash. 358 359 => fsl_mc start mc 580300000 580800000 360 => setenv ethact DPMAC1@xgmii 361 => tftp a0000000 kernel.itb 362 => fsl_mc apply dpl 580700000 363 => bootm a0000000 364 3653. Command sequence for AIOP boot: 366 a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex 367 b) fsl_mc start aiop <FW_addr> - Start AIOP 368 c) fsl_mc apply DPL <DPL_addr> - Apply DPL file 369 d) No DPMAC net-devices are availabe for use in u-boot 370 Please note actual AIOP start will happen during DPL parsing of 371 Management complex 372 373 Example- 374 Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already 375 programmed on NOR flash. 376 377 => fsl_mc start mc 580300000 580800000 378 => fsl_mc start aiop 0x580900000 379 => setenv ethact DPMAC1@xgmii 380 => fsl_mc apply dpl 580700000 381 382Errata A009635 383--------------- 384If the core runs at higher than x3 speed of the platform, there is 385possiblity about sev instruction to getting missed by other cores. 386This is because of SoC Run Control block may not able to sample 387the EVENTI(Sev) signals. 388 389Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to 390wake up A57 cores 391 392Errata workaround uses Env variable "a009635_interval_val". It uses decimal 393value. 394- Default value of env variable is platform clock (MHz) 395 396- User can modify default value by updating the env variable 397 setenv a009635_interval_val 600; saveenv; 398 It configure platform clock as 600 MHz 399 400- Env variable as 0 signifies no workaround 401