1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree file for SolidRun Armada 38x Microsom 4 * 5 * Copyright (C) 2015 Russell King 6 * 7 * This board is in development; the contents of this file work with 8 * the A1 rev 2.0 of the board, which does not represent final 9 * production board. Things will change, don't expect this file to 10 * remain compatible info the future. 11 */ 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 memory { 17 device_type = "memory"; 18 reg = <0x00000000 0x10000000>; /* 256 MB */ 19 }; 20 21 soc { 22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 23 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 24 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000 25 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000 26 MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; 27 28 internal-regs { 29 rtc@a3800 { 30 /* 31 * If the rtc doesn't work, run "date reset" 32 * twice in u-boot. 33 */ 34 status = "okay"; 35 }; 36 }; 37 }; 38}; 39 40ð0 { 41 /* ethernet@70000 */ 42 mac-address = [00 50 43 02 02 01]; 43 pinctrl-0 = <&ge0_rgmii_pins>; 44 pinctrl-names = "default"; 45 phy = <&phy_dedicated>; 46 phy-mode = "rgmii-id"; 47 status = "okay"; 48}; 49 50&mdio { 51 /* 52 * Add the phy clock here, so the phy can be accessed to read its 53 * IDs prior to binding with the driver. 54 */ 55 pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>; 56 pinctrl-names = "default"; 57 58 phy_dedicated: ethernet-phy@0 { 59 /* 60 * Annoyingly, the marvell phy driver configures the LED 61 * register, rather than preserving reset-loaded setting. 62 * We undo that rubbish here. 63 */ 64 marvell,reg-init = <3 16 0 0x101e>; 65 reg = <0>; 66 }; 67}; 68 69&pinctrl { 70 microsom_phy_clk_pins: microsom-phy-clk-pins { 71 marvell,pins = "mpp45"; 72 marvell,function = "ref"; 73 }; 74 /* Optional eMMC */ 75 microsom_sdhci_pins: microsom-sdhci-pins { 76 marvell,pins = "mpp21", "mpp28", "mpp37", 77 "mpp38", "mpp39", "mpp40"; 78 marvell,function = "sd0"; 79 }; 80}; 81 82&spi1 { 83 /* The microsom has an optional W25Q32 on board, connected to CS0 */ 84 pinctrl-0 = <&spi1_pins>; 85 86 w25q32: spi-flash@0 { 87 #address-cells = <1>; 88 #size-cells = <1>; 89 compatible = "w25q32", "jedec,spi-nor"; 90 reg = <0>; /* Chip select 0 */ 91 spi-max-frequency = <3000000>; 92 status = "disabled"; 93 }; 94}; 95 96&uart0 { 97 pinctrl-0 = <&uart0_pins>; 98 pinctrl-names = "default"; 99 status = "okay"; 100 u-boot,dm-pre-reloc; 101}; 102