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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2011
4  * Matthias Weisser <weisserm@arcor.de>
5  *
6  * (C) Copyright 2009 DENX Software Engineering
7  * Author: John Rigby <jrigby@gmail.com>
8  *
9  * Common asm macros for imx25
10  */
11 
12 #ifndef __ASM_ARM_ARCH_MACRO_H__
13 #define __ASM_ARM_ARCH_MACRO_H__
14 #ifdef __ASSEMBLY__
15 
16 #include <asm/arch/imx-regs.h>
17 #include <generated/asm-offsets.h>
18 #include <asm/macro.h>
19 
20 /*
21  * AIPS setup - Only setup MPROTx registers.
22  * The PACR default values are good.
23  *
24  * Default argument values:
25  *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
26  *    user-mode.
27  */
28 .macro init_aips mpr=0x77777777
29 	ldr	r0, =IMX_AIPS1_BASE
30 	ldr	r1, =\mpr
31 	str	r1, [r0, #AIPS_MPR_0_7]
32 	str	r1, [r0, #AIPS_MPR_8_15]
33 	ldr	r2, =IMX_AIPS2_BASE
34 	str	r1, [r2, #AIPS_MPR_0_7]
35 	str	r1, [r2, #AIPS_MPR_8_15]
36 .endm
37 
38 /*
39  * MAX (Multi-Layer AHB Crossbar Switch) setup
40  *
41  * Default argument values:
42  *  - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
43  *  - SGPCR: always park on last master
44  *  - MGPCR: restore default values
45  */
46 .macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
47 	ldr	r0, =IMX_MAX_BASE
48 	ldr	r1, =\mpr
49 	str	r1, [r0, #MAX_MPR0]	/* for S0 */
50 	str	r1, [r0, #MAX_MPR1]	/* for S1 */
51 	str	r1, [r0, #MAX_MPR2]	/* for S2 */
52 	str	r1, [r0, #MAX_MPR3]	/* for S3 */
53 	str	r1, [r0, #MAX_MPR4]	/* for S4 */
54 	ldr	r1, =\sgpcr
55 	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
56 	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
57 	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
58 	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
59 	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
60 	ldr	r1, =\mgpcr
61 	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
62 	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
63 	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
64 	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
65 	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
66 .endm
67 
68 /*
69  * M3IF setup
70  *
71  * Default argument values:
72  *  - CTL:
73  * MRRP[0] = LCDC on priority list (1 << 0)			= 0x00000001
74  * MRRP[1] = MAX1 not on priority list (0 << 1)			= 0x00000000
75  * MRRP[2] = MAX0 not on priority list (0 << 2)			= 0x00000000
76  * MRRP[3] = USBH not on priority list (0 << 3)			= 0x00000000
77  * MRRP[4] = SDMA not on priority list (0 << 4)			= 0x00000000
78  * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5)	= 0x00000000
79  * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6)	= 0x00000000
80  * MRRP[7] = CSI not on priority list (0 << 7)			= 0x00000000
81  *								------------
82  *								  0x00000001
83  */
84 .macro init_m3if ctl=0x00000001
85 	/* M3IF Control Register (M3IFCTL) */
86 	write32	IMX_M3IF_CTRL_BASE, \ctl
87 .endm
88 
89 #endif /* __ASSEMBLY__ */
90 #endif /* __ASM_ARM_ARCH_MACRO_H__ */
91