1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 SAMSUNG Electronics 4 * Minkyu Kang <mk7.kang@samsung.com> 5 * Portions Copyright (C) 2011-2012 NVIDIA Corporation 6 */ 7 8 #ifndef __TEGRA_MMC_H_ 9 #define __TEGRA_MMC_H_ 10 11 #include <common.h> 12 #include <clk.h> 13 #include <reset.h> 14 #include <fdtdec.h> 15 #include <asm/gpio.h> 16 17 /* for mmc_config definition */ 18 #include <mmc.h> 19 20 #ifndef __ASSEMBLY__ 21 struct tegra_mmc { 22 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */ 23 unsigned short blksize; /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */ 24 unsigned short blkcnt; /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */ 25 unsigned int argument; /* _ARGUMENT_0 */ 26 unsigned short trnmod; /* _CMD_XFER_MODE_0 15:00 xfer mode */ 27 unsigned short cmdreg; /* _CMD_XFER_MODE_0 31:16 cmd reg */ 28 unsigned int rspreg0; /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */ 29 unsigned int rspreg1; /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */ 30 unsigned int rspreg2; /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */ 31 unsigned int rspreg3; /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */ 32 unsigned int bdata; /* _BUFFER_DATA_PORT_0 */ 33 unsigned int prnsts; /* _PRESENT_STATE_0 */ 34 unsigned char hostctl; /* _POWER_CONTROL_HOST_0 7:00 */ 35 unsigned char pwrcon; /* _POWER_CONTROL_HOST_0 15:8 */ 36 unsigned char blkgap; /* _POWER_CONTROL_HOST_9 23:16 */ 37 unsigned char wakcon; /* _POWER_CONTROL_HOST_0 31:24 */ 38 unsigned short clkcon; /* _CLOCK_CONTROL_0 15:00 */ 39 unsigned char timeoutcon; /* _TIMEOUT_CTRL 23:16 */ 40 unsigned char swrst; /* _SW_RESET_ 31:24 */ 41 unsigned int norintsts; /* _INTERRUPT_STATUS_0 */ 42 unsigned int norintstsen; /* _INTERRUPT_STATUS_ENABLE_0 */ 43 unsigned int norintsigen; /* _INTERRUPT_SIGNAL_ENABLE_0 */ 44 unsigned short acmd12errsts; /* _AUTO_CMD12_ERR_STATUS_0 15:00 */ 45 unsigned char res1[2]; /* _RESERVED 31:16 */ 46 unsigned int capareg; /* _CAPABILITIES_0 */ 47 unsigned char res2[4]; /* RESERVED, offset 44h-47h */ 48 unsigned int maxcurr; /* _MAXIMUM_CURRENT_0 */ 49 unsigned char res3[4]; /* RESERVED, offset 4Ch-4Fh */ 50 unsigned short setacmd12err; /* offset 50h */ 51 unsigned short setinterr; /* offset 52h */ 52 unsigned char admaerr; /* offset 54h */ 53 unsigned char res4[3]; /* RESERVED, offset 55h-57h */ 54 unsigned long admaaddr; /* offset 58h-5Fh */ 55 unsigned char res5[0xa0]; /* RESERVED, offset 60h-FBh */ 56 unsigned short slotintstatus; /* offset FCh */ 57 unsigned short hcver; /* HOST Version */ 58 unsigned int venclkctl; /* _VENDOR_CLOCK_CNTRL_0, 100h */ 59 unsigned int venspictl; /* _VENDOR_SPI_CNTRL_0, 104h */ 60 unsigned int venspiintsts; /* _VENDOR_SPI_INT_STATUS_0, 108h */ 61 unsigned int venceatactl; /* _VENDOR_CEATA_CNTRL_0, 10Ch */ 62 unsigned int venbootctl; /* _VENDOR_BOOT_CNTRL_0, 110h */ 63 unsigned int venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */ 64 unsigned int venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */ 65 unsigned int vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */ 66 unsigned int venmiscctl; /* _VENDOR_MISC_CNTRL_0, 120h */ 67 unsigned int res6[47]; /* 0x124 ~ 0x1DC */ 68 unsigned int sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0, 1E0h */ 69 unsigned int autocalcfg; /* _AUTO_CAL_CONFIG_0, 1E4h */ 70 unsigned int autocalintval; /* _AUTO_CAL_INTERVAL_0, 1E8h */ 71 unsigned int autocalsts; /* _AUTO_CAL_STATUS_0, 1ECh */ 72 }; 73 74 #define TEGRA_MMC_PWRCTL_SD_BUS_POWER (1 << 0) 75 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 (5 << 1) 76 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 (6 << 1) 77 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 (7 << 1) 78 79 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3) 80 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3) 81 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3) 82 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3) 83 84 #define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0) 85 #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1) 86 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4) 87 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4) 88 #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5) 89 90 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0) 91 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0) 92 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0) 93 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0) 94 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0) 95 96 #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3) 97 #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4) 98 #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5) 99 100 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0) 101 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1) 102 103 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0) 104 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1) 105 #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2) 106 107 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8 108 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8) 109 110 #define TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK (1 << 17) 111 112 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0) 113 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1) 114 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2) 115 116 #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0) 117 #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1) 118 #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3) 119 #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15) 120 #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16) 121 122 #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0) 123 #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1) 124 #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3) 125 #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4) 126 #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5) 127 128 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1) 129 130 /* SDMMC1/3 settings from section 24.6 of T30 TRM */ 131 #define MEMCOMP_PADCTRL_VREF 7 132 #define AUTO_CAL_ENABLED (1 << 29) 133 #define AUTO_CAL_PD_OFFSET (0x70 << 8) 134 #define AUTO_CAL_PU_OFFSET (0x62 << 0) 135 136 #endif /* __ASSEMBLY__ */ 137 #endif /* __TEGRA_MMC_H_ */ 138