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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4  */
5 
6 #ifndef _TEGRA114_PINMUX_H_
7 #define _TEGRA114_PINMUX_H_
8 
9 enum pmux_pingrp {
10 	PMUX_PINGRP_ULPI_DATA0_PO1,
11 	PMUX_PINGRP_ULPI_DATA1_PO2,
12 	PMUX_PINGRP_ULPI_DATA2_PO3,
13 	PMUX_PINGRP_ULPI_DATA3_PO4,
14 	PMUX_PINGRP_ULPI_DATA4_PO5,
15 	PMUX_PINGRP_ULPI_DATA5_PO6,
16 	PMUX_PINGRP_ULPI_DATA6_PO7,
17 	PMUX_PINGRP_ULPI_DATA7_PO0,
18 	PMUX_PINGRP_ULPI_CLK_PY0,
19 	PMUX_PINGRP_ULPI_DIR_PY1,
20 	PMUX_PINGRP_ULPI_NXT_PY2,
21 	PMUX_PINGRP_ULPI_STP_PY3,
22 	PMUX_PINGRP_DAP3_FS_PP0,
23 	PMUX_PINGRP_DAP3_DIN_PP1,
24 	PMUX_PINGRP_DAP3_DOUT_PP2,
25 	PMUX_PINGRP_DAP3_SCLK_PP3,
26 	PMUX_PINGRP_PV0,
27 	PMUX_PINGRP_PV1,
28 	PMUX_PINGRP_SDMMC1_CLK_PZ0,
29 	PMUX_PINGRP_SDMMC1_CMD_PZ1,
30 	PMUX_PINGRP_SDMMC1_DAT3_PY4,
31 	PMUX_PINGRP_SDMMC1_DAT2_PY5,
32 	PMUX_PINGRP_SDMMC1_DAT1_PY6,
33 	PMUX_PINGRP_SDMMC1_DAT0_PY7,
34 	PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
35 	PMUX_PINGRP_CLK2_REQ_PCC5,
36 	PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
37 	PMUX_PINGRP_DDC_SCL_PV4,
38 	PMUX_PINGRP_DDC_SDA_PV5,
39 	PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
40 	PMUX_PINGRP_UART2_TXD_PC2,
41 	PMUX_PINGRP_UART2_RTS_N_PJ6,
42 	PMUX_PINGRP_UART2_CTS_N_PJ5,
43 	PMUX_PINGRP_UART3_TXD_PW6,
44 	PMUX_PINGRP_UART3_RXD_PW7,
45 	PMUX_PINGRP_UART3_CTS_N_PA1,
46 	PMUX_PINGRP_UART3_RTS_N_PC0,
47 	PMUX_PINGRP_PU0,
48 	PMUX_PINGRP_PU1,
49 	PMUX_PINGRP_PU2,
50 	PMUX_PINGRP_PU3,
51 	PMUX_PINGRP_PU4,
52 	PMUX_PINGRP_PU5,
53 	PMUX_PINGRP_PU6,
54 	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
55 	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
56 	PMUX_PINGRP_DAP4_FS_PP4,
57 	PMUX_PINGRP_DAP4_DIN_PP5,
58 	PMUX_PINGRP_DAP4_DOUT_PP6,
59 	PMUX_PINGRP_DAP4_SCLK_PP7,
60 	PMUX_PINGRP_CLK3_OUT_PEE0,
61 	PMUX_PINGRP_CLK3_REQ_PEE1,
62 	PMUX_PINGRP_GMI_WP_N_PC7,
63 	PMUX_PINGRP_GMI_IORDY_PI5,
64 	PMUX_PINGRP_GMI_WAIT_PI7,
65 	PMUX_PINGRP_GMI_ADV_N_PK0,
66 	PMUX_PINGRP_GMI_CLK_PK1,
67 	PMUX_PINGRP_GMI_CS0_N_PJ0,
68 	PMUX_PINGRP_GMI_CS1_N_PJ2,
69 	PMUX_PINGRP_GMI_CS2_N_PK3,
70 	PMUX_PINGRP_GMI_CS3_N_PK4,
71 	PMUX_PINGRP_GMI_CS4_N_PK2,
72 	PMUX_PINGRP_GMI_CS6_N_PI3,
73 	PMUX_PINGRP_GMI_CS7_N_PI6,
74 	PMUX_PINGRP_GMI_AD0_PG0,
75 	PMUX_PINGRP_GMI_AD1_PG1,
76 	PMUX_PINGRP_GMI_AD2_PG2,
77 	PMUX_PINGRP_GMI_AD3_PG3,
78 	PMUX_PINGRP_GMI_AD4_PG4,
79 	PMUX_PINGRP_GMI_AD5_PG5,
80 	PMUX_PINGRP_GMI_AD6_PG6,
81 	PMUX_PINGRP_GMI_AD7_PG7,
82 	PMUX_PINGRP_GMI_AD8_PH0,
83 	PMUX_PINGRP_GMI_AD9_PH1,
84 	PMUX_PINGRP_GMI_AD10_PH2,
85 	PMUX_PINGRP_GMI_AD11_PH3,
86 	PMUX_PINGRP_GMI_AD12_PH4,
87 	PMUX_PINGRP_GMI_AD13_PH5,
88 	PMUX_PINGRP_GMI_AD14_PH6,
89 	PMUX_PINGRP_GMI_AD15_PH7,
90 	PMUX_PINGRP_GMI_A16_PJ7,
91 	PMUX_PINGRP_GMI_A17_PB0,
92 	PMUX_PINGRP_GMI_A18_PB1,
93 	PMUX_PINGRP_GMI_A19_PK7,
94 	PMUX_PINGRP_GMI_WR_N_PI0,
95 	PMUX_PINGRP_GMI_OE_N_PI1,
96 	PMUX_PINGRP_GMI_DQS_P_PJ3,
97 	PMUX_PINGRP_GMI_RST_N_PI4,
98 	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
99 	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
100 	PMUX_PINGRP_SDMMC4_CLK_PCC4,
101 	PMUX_PINGRP_SDMMC4_CMD_PT7,
102 	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
103 	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
104 	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
105 	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
106 	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
107 	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
108 	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
109 	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
110 	PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
111 	PMUX_PINGRP_PCC1,
112 	PMUX_PINGRP_PBB0,
113 	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
114 	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
115 	PMUX_PINGRP_PBB3,
116 	PMUX_PINGRP_PBB4,
117 	PMUX_PINGRP_PBB5,
118 	PMUX_PINGRP_PBB6,
119 	PMUX_PINGRP_PBB7,
120 	PMUX_PINGRP_PCC2,
121 	PMUX_PINGRP_JTAG_RTCK,
122 	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
123 	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
124 	PMUX_PINGRP_KB_ROW0_PR0,
125 	PMUX_PINGRP_KB_ROW1_PR1,
126 	PMUX_PINGRP_KB_ROW2_PR2,
127 	PMUX_PINGRP_KB_ROW3_PR3,
128 	PMUX_PINGRP_KB_ROW4_PR4,
129 	PMUX_PINGRP_KB_ROW5_PR5,
130 	PMUX_PINGRP_KB_ROW6_PR6,
131 	PMUX_PINGRP_KB_ROW7_PR7,
132 	PMUX_PINGRP_KB_ROW8_PS0,
133 	PMUX_PINGRP_KB_ROW9_PS1,
134 	PMUX_PINGRP_KB_ROW10_PS2,
135 	PMUX_PINGRP_KB_COL0_PQ0 = (0x2fc / 4),
136 	PMUX_PINGRP_KB_COL1_PQ1,
137 	PMUX_PINGRP_KB_COL2_PQ2,
138 	PMUX_PINGRP_KB_COL3_PQ3,
139 	PMUX_PINGRP_KB_COL4_PQ4,
140 	PMUX_PINGRP_KB_COL5_PQ5,
141 	PMUX_PINGRP_KB_COL6_PQ6,
142 	PMUX_PINGRP_KB_COL7_PQ7,
143 	PMUX_PINGRP_CLK_32K_OUT_PA0,
144 	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
145 	PMUX_PINGRP_CORE_PWR_REQ,
146 	PMUX_PINGRP_CPU_PWR_REQ,
147 	PMUX_PINGRP_PWR_INT_N,
148 	PMUX_PINGRP_CLK_32K_IN,
149 	PMUX_PINGRP_OWR,
150 	PMUX_PINGRP_DAP1_FS_PN0,
151 	PMUX_PINGRP_DAP1_DIN_PN1,
152 	PMUX_PINGRP_DAP1_DOUT_PN2,
153 	PMUX_PINGRP_DAP1_SCLK_PN3,
154 	PMUX_PINGRP_CLK1_REQ_PEE2,
155 	PMUX_PINGRP_CLK1_OUT_PW4,
156 	PMUX_PINGRP_SPDIF_IN_PK6,
157 	PMUX_PINGRP_SPDIF_OUT_PK5,
158 	PMUX_PINGRP_DAP2_FS_PA2,
159 	PMUX_PINGRP_DAP2_DIN_PA4,
160 	PMUX_PINGRP_DAP2_DOUT_PA5,
161 	PMUX_PINGRP_DAP2_SCLK_PA3,
162 	PMUX_PINGRP_DVFS_PWM_PX0,
163 	PMUX_PINGRP_GPIO_X1_AUD_PX1,
164 	PMUX_PINGRP_GPIO_X3_AUD_PX3,
165 	PMUX_PINGRP_DVFS_CLK_PX2,
166 	PMUX_PINGRP_GPIO_X4_AUD_PX4,
167 	PMUX_PINGRP_GPIO_X5_AUD_PX5,
168 	PMUX_PINGRP_GPIO_X6_AUD_PX6,
169 	PMUX_PINGRP_GPIO_X7_AUD_PX7,
170 	PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
171 	PMUX_PINGRP_SDMMC3_CMD_PA7,
172 	PMUX_PINGRP_SDMMC3_DAT0_PB7,
173 	PMUX_PINGRP_SDMMC3_DAT1_PB6,
174 	PMUX_PINGRP_SDMMC3_DAT2_PB5,
175 	PMUX_PINGRP_SDMMC3_DAT3_PB4,
176 	PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
177 	PMUX_PINGRP_SDMMC1_WP_N_PV3,
178 	PMUX_PINGRP_SDMMC3_CD_N_PV2,
179 	PMUX_PINGRP_GPIO_W2_AUD_PW2,
180 	PMUX_PINGRP_GPIO_W3_AUD_PW3,
181 	PMUX_PINGRP_USB_VBUS_EN0_PN4,
182 	PMUX_PINGRP_USB_VBUS_EN1_PN5,
183 	PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
184 	PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
185 	PMUX_PINGRP_GMI_CLK_LB,
186 	PMUX_PINGRP_RESET_OUT_N,
187 	PMUX_PINGRP_COUNT,
188 };
189 
190 enum pmux_drvgrp {
191 	PMUX_DRVGRP_AO1,
192 	PMUX_DRVGRP_AO2,
193 	PMUX_DRVGRP_AT1,
194 	PMUX_DRVGRP_AT2,
195 	PMUX_DRVGRP_AT3,
196 	PMUX_DRVGRP_AT4,
197 	PMUX_DRVGRP_AT5,
198 	PMUX_DRVGRP_CDEV1,
199 	PMUX_DRVGRP_CDEV2,
200 	PMUX_DRVGRP_DAP1 = (0x28 / 4),
201 	PMUX_DRVGRP_DAP2,
202 	PMUX_DRVGRP_DAP3,
203 	PMUX_DRVGRP_DAP4,
204 	PMUX_DRVGRP_DBG,
205 	PMUX_DRVGRP_SDIO3 = (0x48 / 4),
206 	PMUX_DRVGRP_SPI,
207 	PMUX_DRVGRP_UAA,
208 	PMUX_DRVGRP_UAB,
209 	PMUX_DRVGRP_UART2,
210 	PMUX_DRVGRP_UART3,
211 	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
212 	PMUX_DRVGRP_DDC = (0x94 / 4),
213 	PMUX_DRVGRP_GMA,
214 	PMUX_DRVGRP_GME = (0xa8 / 4),
215 	PMUX_DRVGRP_GMF,
216 	PMUX_DRVGRP_GMG,
217 	PMUX_DRVGRP_GMH,
218 	PMUX_DRVGRP_OWR,
219 	PMUX_DRVGRP_UDA,
220 	PMUX_DRVGRP_DEV3 = (0xc4 / 4),
221 	PMUX_DRVGRP_CEC = (0xd0 / 4),
222 	PMUX_DRVGRP_AT6 = (0x12c / 4),
223 	PMUX_DRVGRP_DAP5,
224 	PMUX_DRVGRP_USB_VBUS_EN,
225 	PMUX_DRVGRP_AO3,
226 	PMUX_DRVGRP_HV0,
227 	PMUX_DRVGRP_SDIO4,
228 	PMUX_DRVGRP_AO0,
229 	PMUX_DRVGRP_COUNT,
230 };
231 
232 enum pmux_func {
233 	PMUX_FUNC_DEFAULT,
234 	PMUX_FUNC_BLINK,
235 	PMUX_FUNC_CEC,
236 	PMUX_FUNC_CLDVFS,
237 	PMUX_FUNC_CLK,
238 	PMUX_FUNC_CLK12,
239 	PMUX_FUNC_CPU,
240 	PMUX_FUNC_DAP,
241 	PMUX_FUNC_DAP1,
242 	PMUX_FUNC_DAP2,
243 	PMUX_FUNC_DEV3,
244 	PMUX_FUNC_DISPLAYA,
245 	PMUX_FUNC_DISPLAYA_ALT,
246 	PMUX_FUNC_DISPLAYB,
247 	PMUX_FUNC_DTV,
248 	PMUX_FUNC_EMC_DLL,
249 	PMUX_FUNC_EXTPERIPH1,
250 	PMUX_FUNC_EXTPERIPH2,
251 	PMUX_FUNC_EXTPERIPH3,
252 	PMUX_FUNC_GMI,
253 	PMUX_FUNC_GMI_ALT,
254 	PMUX_FUNC_HDA,
255 	PMUX_FUNC_HSI,
256 	PMUX_FUNC_I2C1,
257 	PMUX_FUNC_I2C2,
258 	PMUX_FUNC_I2C3,
259 	PMUX_FUNC_I2C4,
260 	PMUX_FUNC_I2CPWR,
261 	PMUX_FUNC_I2S0,
262 	PMUX_FUNC_I2S1,
263 	PMUX_FUNC_I2S2,
264 	PMUX_FUNC_I2S3,
265 	PMUX_FUNC_I2S4,
266 	PMUX_FUNC_IRDA,
267 	PMUX_FUNC_KBC,
268 	PMUX_FUNC_NAND,
269 	PMUX_FUNC_NAND_ALT,
270 	PMUX_FUNC_OWR,
271 	PMUX_FUNC_PMI,
272 	PMUX_FUNC_PWM0,
273 	PMUX_FUNC_PWM1,
274 	PMUX_FUNC_PWM2,
275 	PMUX_FUNC_PWM3,
276 	PMUX_FUNC_PWRON,
277 	PMUX_FUNC_RESET_OUT_N,
278 	PMUX_FUNC_RTCK,
279 	PMUX_FUNC_SDMMC1,
280 	PMUX_FUNC_SDMMC2,
281 	PMUX_FUNC_SDMMC3,
282 	PMUX_FUNC_SDMMC4,
283 	PMUX_FUNC_SOC,
284 	PMUX_FUNC_SPDIF,
285 	PMUX_FUNC_SPI1,
286 	PMUX_FUNC_SPI2,
287 	PMUX_FUNC_SPI3,
288 	PMUX_FUNC_SPI4,
289 	PMUX_FUNC_SPI5,
290 	PMUX_FUNC_SPI6,
291 	PMUX_FUNC_SYSCLK,
292 	PMUX_FUNC_TRACE,
293 	PMUX_FUNC_UARTA,
294 	PMUX_FUNC_UARTB,
295 	PMUX_FUNC_UARTC,
296 	PMUX_FUNC_UARTD,
297 	PMUX_FUNC_ULPI,
298 	PMUX_FUNC_USB,
299 	PMUX_FUNC_VGP1,
300 	PMUX_FUNC_VGP2,
301 	PMUX_FUNC_VGP3,
302 	PMUX_FUNC_VGP4,
303 	PMUX_FUNC_VGP5,
304 	PMUX_FUNC_VGP6,
305 	PMUX_FUNC_VI,
306 	PMUX_FUNC_VI_ALT1,
307 	PMUX_FUNC_VI_ALT3,
308 	PMUX_FUNC_RSVD1,
309 	PMUX_FUNC_RSVD2,
310 	PMUX_FUNC_RSVD3,
311 	PMUX_FUNC_RSVD4,
312 	PMUX_FUNC_COUNT,
313 };
314 
315 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
316 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
317 #define TEGRA_PMX_SOC_HAS_DRVGRPS
318 #define TEGRA_PMX_GRPS_HAVE_LPMD
319 #define TEGRA_PMX_GRPS_HAVE_SCHMT
320 #define TEGRA_PMX_GRPS_HAVE_HSM
321 #define TEGRA_PMX_PINS_HAVE_E_INPUT
322 #define TEGRA_PMX_PINS_HAVE_LOCK
323 #define TEGRA_PMX_PINS_HAVE_OD
324 #define TEGRA_PMX_PINS_HAVE_IO_RESET
325 #define TEGRA_PMX_PINS_HAVE_RCV_SEL
326 #include <asm/arch-tegra/pinmux.h>
327 
328 #endif /* _TEGRA114_PINMUX_H_ */
329