1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <asm/armv7.h>
8 #include <asm/pl310.h>
9 #include <asm/io.h>
10 #include <asm/mach-imx/sys_proto.h>
11
enable_ca7_smp(void)12 static void enable_ca7_smp(void)
13 {
14 u32 val;
15
16 /* Read MIDR */
17 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(val));
18 val = (val >> 4);
19 val &= 0xf;
20
21 /* Only set the SMP for Cortex A7 */
22 if (val == 0x7) {
23 /* Read auxiliary control register */
24 asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
25
26 if (val & (1 << 6))
27 return;
28
29 /* Enable SMP */
30 val |= (1 << 6);
31
32 /* Write auxiliary control register */
33 asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
34
35 DSB;
36 ISB;
37 }
38 }
39
40 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)41 void enable_caches(void)
42 {
43 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
44 enum dcache_option option = DCACHE_WRITETHROUGH;
45 #else
46 enum dcache_option option = DCACHE_WRITEBACK;
47 #endif
48 /* Avoid random hang when download by usb */
49 invalidate_dcache_all();
50
51 /* Set ACTLR.SMP bit for Cortex-A7 */
52 enable_ca7_smp();
53
54 /* Enable D-cache. I-cache is already enabled in start.S */
55 dcache_enable();
56
57 /* Enable caching on OCRAM and ROM */
58 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
59 ROMCP_ARB_END_ADDR,
60 option);
61 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
62 IRAM_SIZE,
63 option);
64 }
65 #else
enable_caches(void)66 void enable_caches(void)
67 {
68 /*
69 * Set ACTLR.SMP bit for Cortex-A7, even if the caches are
70 * disabled by u-boot
71 */
72 enable_ca7_smp();
73
74 puts("WARNING: Caches not enabled\n");
75 }
76 #endif
77
78 #ifndef CONFIG_SYS_L2CACHE_OFF
79 #ifdef CONFIG_SYS_L2_PL310
80 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
v7_outer_cache_enable(void)81 void v7_outer_cache_enable(void)
82 {
83 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
84 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
85 unsigned int val;
86
87
88 /*
89 * Must disable the L2 before changing the latency parameters
90 * and auxiliary control register.
91 */
92 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
93
94 /*
95 * Set bit 22 in the auxiliary control register. If this bit
96 * is cleared, PL310 treats Normal Shared Non-cacheable
97 * accesses as Cacheable no-allocate.
98 */
99 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
100
101 if (is_mx6sl() || is_mx6sll()) {
102 val = readl(&iomux->gpr[11]);
103 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
104 /* L2 cache configured as OCRAM, reset it */
105 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
106 writel(val, &iomux->gpr[11]);
107 }
108 }
109
110 writel(0x132, &pl310->pl310_tag_latency_ctrl);
111 writel(0x132, &pl310->pl310_data_latency_ctrl);
112
113 val = readl(&pl310->pl310_prefetch_ctrl);
114
115 /* Turn on the L2 I/D prefetch */
116 val |= 0x30000000;
117
118 /*
119 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
120 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
121 * But according to ARM PL310 errata: 752271
122 * ID: 752271: Double linefill feature can cause data corruption
123 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
124 * Workaround: The only workaround to this erratum is to disable the
125 * double linefill feature. This is the default behavior.
126 */
127
128 #ifndef CONFIG_MX6Q
129 val |= 0x40800000;
130 #endif
131 writel(val, &pl310->pl310_prefetch_ctrl);
132
133 val = readl(&pl310->pl310_power_ctrl);
134 val |= L2X0_DYNAMIC_CLK_GATING_EN;
135 val |= L2X0_STNDBY_MODE_EN;
136 writel(val, &pl310->pl310_power_ctrl);
137
138 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
139 }
140
v7_outer_cache_disable(void)141 void v7_outer_cache_disable(void)
142 {
143 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
144
145 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
146 }
147 #endif /* !CONFIG_SYS_L2_PL310 */
148 #endif /* !CONFIG_SYS_L2CACHE_OFF */
149