1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007
4 * Sascha Hauer, Pengutronix
5 *
6 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 */
8
9 #include <common.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/sys_proto.h>
13
14 #include <linux/errno.h>
15 #include <asm/io.h>
16 #include <asm/mach-imx/boot_mode.h>
17
18 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
19 #error "CPU_TYPE not defined"
20 #endif
21
get_cpu_rev(void)22 u32 get_cpu_rev(void)
23 {
24 #ifdef CONFIG_MX51
25 int system_rev = 0x51000;
26 #else
27 int system_rev = 0x53000;
28 #endif
29 int reg = __raw_readl(ROM_SI_REV);
30
31 #if defined(CONFIG_MX51)
32 switch (reg) {
33 case 0x02:
34 system_rev |= CHIP_REV_1_1;
35 break;
36 case 0x10:
37 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
38 system_rev |= CHIP_REV_2_5;
39 else
40 system_rev |= CHIP_REV_2_0;
41 break;
42 case 0x20:
43 system_rev |= CHIP_REV_3_0;
44 break;
45 default:
46 system_rev |= CHIP_REV_1_0;
47 break;
48 }
49 #else
50 if (reg < 0x20)
51 system_rev |= CHIP_REV_1_0;
52 else
53 system_rev |= reg;
54 #endif
55 return system_rev;
56 }
57
58 #ifdef CONFIG_REVISION_TAG
get_board_rev(void)59 u32 __weak get_board_rev(void)
60 {
61 return get_cpu_rev();
62 }
63 #endif
64
65 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)66 void enable_caches(void)
67 {
68 /* Enable D-cache. I-cache is already enabled in start.S */
69 dcache_enable();
70 }
71 #endif
72
73 #if defined(CONFIG_FEC_MXC)
imx_get_mac_from_fuse(int dev_id,unsigned char * mac)74 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
75 {
76 int i;
77 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
78 struct fuse_bank *bank = &iim->bank[1];
79 struct fuse_bank1_regs *fuse =
80 (struct fuse_bank1_regs *)bank->fuse_regs;
81
82 for (i = 0; i < 6; i++)
83 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
84 }
85 #endif
86
87 #ifdef CONFIG_MX53
boot_mode_apply(unsigned cfg_val)88 void boot_mode_apply(unsigned cfg_val)
89 {
90 writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
91 }
92 /*
93 * cfg_val will be used for
94 * Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
95 *
96 * If bit 28 of LPGR is set upon watchdog reset,
97 * bits[25:0] of LPGR will move to SBMR.
98 */
99 const struct boot_mode soc_boot_modes[] = {
100 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
101 /* usb or serial download */
102 {"usb", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x13)},
103 {"sata", MAKE_CFGVAL(0x28, 0x00, 0x00, 0x12)},
104 {"escpi1:0", MAKE_CFGVAL(0x38, 0x20, 0x00, 0x12)},
105 {"escpi1:1", MAKE_CFGVAL(0x38, 0x20, 0x04, 0x12)},
106 {"escpi1:2", MAKE_CFGVAL(0x38, 0x20, 0x08, 0x12)},
107 {"escpi1:3", MAKE_CFGVAL(0x38, 0x20, 0x0c, 0x12)},
108 /* 4 bit bus width */
109 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
110 {"esdhc2", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
111 {"esdhc3", MAKE_CFGVAL(0x40, 0x20, 0x10, 0x12)},
112 {"esdhc4", MAKE_CFGVAL(0x40, 0x20, 0x18, 0x12)},
113 {NULL, 0},
114 };
115 #endif
116