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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * HW regs data for OMAP4
5  *
6  * (C) Copyright 2013
7  * Texas Instruments, <www.ti.com>
8  *
9  * Sricharan R <r.sricharan@ti.com>
10  */
11 
12 #include <asm/omap_common.h>
13 
14 struct prcm_regs const omap4_prcm = {
15 	/* cm1.ckgen */
16 	.cm_clksel_core  = 0x4a004100,
17 	.cm_clksel_abe = 0x4a004108,
18 	.cm_dll_ctrl = 0x4a004110,
19 	.cm_clkmode_dpll_core = 0x4a004120,
20 	.cm_idlest_dpll_core = 0x4a004124,
21 	.cm_autoidle_dpll_core = 0x4a004128,
22 	.cm_clksel_dpll_core = 0x4a00412c,
23 	.cm_div_m2_dpll_core = 0x4a004130,
24 	.cm_div_m3_dpll_core = 0x4a004134,
25 	.cm_div_m4_dpll_core = 0x4a004138,
26 	.cm_div_m5_dpll_core = 0x4a00413c,
27 	.cm_div_m6_dpll_core = 0x4a004140,
28 	.cm_div_m7_dpll_core = 0x4a004144,
29 	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
30 	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
31 	.cm_emu_override_dpll_core = 0x4a004150,
32 	.cm_clkmode_dpll_mpu = 0x4a004160,
33 	.cm_idlest_dpll_mpu = 0x4a004164,
34 	.cm_autoidle_dpll_mpu = 0x4a004168,
35 	.cm_clksel_dpll_mpu = 0x4a00416c,
36 	.cm_div_m2_dpll_mpu = 0x4a004170,
37 	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
38 	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
39 	.cm_bypclk_dpll_mpu = 0x4a00419c,
40 	.cm_clkmode_dpll_iva = 0x4a0041a0,
41 	.cm_idlest_dpll_iva = 0x4a0041a4,
42 	.cm_autoidle_dpll_iva = 0x4a0041a8,
43 	.cm_clksel_dpll_iva = 0x4a0041ac,
44 	.cm_div_m4_dpll_iva = 0x4a0041b8,
45 	.cm_div_m5_dpll_iva = 0x4a0041bc,
46 	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
47 	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
48 	.cm_bypclk_dpll_iva = 0x4a0041dc,
49 	.cm_clkmode_dpll_abe = 0x4a0041e0,
50 	.cm_idlest_dpll_abe = 0x4a0041e4,
51 	.cm_autoidle_dpll_abe = 0x4a0041e8,
52 	.cm_clksel_dpll_abe = 0x4a0041ec,
53 	.cm_div_m2_dpll_abe = 0x4a0041f0,
54 	.cm_div_m3_dpll_abe = 0x4a0041f4,
55 	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
56 	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
57 	.cm_clkmode_dpll_ddrphy = 0x4a004220,
58 	.cm_idlest_dpll_ddrphy = 0x4a004224,
59 	.cm_autoidle_dpll_ddrphy = 0x4a004228,
60 	.cm_clksel_dpll_ddrphy = 0x4a00422c,
61 	.cm_div_m2_dpll_ddrphy = 0x4a004230,
62 	.cm_div_m4_dpll_ddrphy = 0x4a004238,
63 	.cm_div_m5_dpll_ddrphy = 0x4a00423c,
64 	.cm_div_m6_dpll_ddrphy = 0x4a004240,
65 	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
66 	.cm_shadow_freq_config1 = 0x4a004260,
67 	.cm_mpu_mpu_clkctrl = 0x4a004320,
68 
69 	/* cm1.dsp */
70 	.cm_dsp_clkstctrl = 0x4a004400,
71 	.cm_dsp_dsp_clkctrl = 0x4a004420,
72 
73 	/* cm1.abe */
74 	.cm1_abe_clkstctrl = 0x4a004500,
75 	.cm1_abe_l4abe_clkctrl = 0x4a004520,
76 	.cm1_abe_aess_clkctrl = 0x4a004528,
77 	.cm1_abe_pdm_clkctrl = 0x4a004530,
78 	.cm1_abe_dmic_clkctrl = 0x4a004538,
79 	.cm1_abe_mcasp_clkctrl = 0x4a004540,
80 	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
81 	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
82 	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
83 	.cm1_abe_slimbus_clkctrl = 0x4a004560,
84 	.cm1_abe_timer5_clkctrl = 0x4a004568,
85 	.cm1_abe_timer6_clkctrl = 0x4a004570,
86 	.cm1_abe_timer7_clkctrl = 0x4a004578,
87 	.cm1_abe_timer8_clkctrl = 0x4a004580,
88 	.cm1_abe_wdt3_clkctrl = 0x4a004588,
89 
90 	/* cm2.ckgen */
91 	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
92 	.cm_clksel_usb_60mhz = 0x4a008104,
93 	.cm_scale_fclk = 0x4a008108,
94 	.cm_core_dvfs_perf1 = 0x4a008110,
95 	.cm_core_dvfs_perf2 = 0x4a008114,
96 	.cm_core_dvfs_perf3 = 0x4a008118,
97 	.cm_core_dvfs_perf4 = 0x4a00811c,
98 	.cm_core_dvfs_current = 0x4a008124,
99 	.cm_iva_dvfs_perf_tesla = 0x4a008128,
100 	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
101 	.cm_iva_dvfs_perf_abe = 0x4a008130,
102 	.cm_iva_dvfs_current = 0x4a008138,
103 	.cm_clkmode_dpll_per = 0x4a008140,
104 	.cm_idlest_dpll_per = 0x4a008144,
105 	.cm_autoidle_dpll_per = 0x4a008148,
106 	.cm_clksel_dpll_per = 0x4a00814c,
107 	.cm_div_m2_dpll_per = 0x4a008150,
108 	.cm_div_m3_dpll_per = 0x4a008154,
109 	.cm_div_m4_dpll_per = 0x4a008158,
110 	.cm_div_m5_dpll_per = 0x4a00815c,
111 	.cm_div_m6_dpll_per = 0x4a008160,
112 	.cm_div_m7_dpll_per = 0x4a008164,
113 	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
114 	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
115 	.cm_emu_override_dpll_per = 0x4a008170,
116 	.cm_clkmode_dpll_usb = 0x4a008180,
117 	.cm_idlest_dpll_usb = 0x4a008184,
118 	.cm_autoidle_dpll_usb = 0x4a008188,
119 	.cm_clksel_dpll_usb = 0x4a00818c,
120 	.cm_div_m2_dpll_usb = 0x4a008190,
121 	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
122 	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
123 	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
124 	.cm_clkmode_dpll_unipro = 0x4a0081c0,
125 	.cm_idlest_dpll_unipro = 0x4a0081c4,
126 	.cm_autoidle_dpll_unipro = 0x4a0081c8,
127 	.cm_clksel_dpll_unipro = 0x4a0081cc,
128 	.cm_div_m2_dpll_unipro = 0x4a0081d0,
129 	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
130 	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
131 	.cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640,
132 
133 	/* cm2.core */
134 	.cm_l3_1_clkstctrl = 0x4a008700,
135 	.cm_l3_1_dynamicdep = 0x4a008708,
136 	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
137 	.cm_l3_2_clkstctrl = 0x4a008800,
138 	.cm_l3_2_dynamicdep = 0x4a008808,
139 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
140 	.cm_l3_gpmc_clkctrl = 0x4a008828,
141 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
142 	.cm_mpu_m3_clkstctrl = 0x4a008900,
143 	.cm_mpu_m3_staticdep = 0x4a008904,
144 	.cm_mpu_m3_dynamicdep = 0x4a008908,
145 	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
146 	.cm_sdma_clkstctrl = 0x4a008a00,
147 	.cm_sdma_staticdep = 0x4a008a04,
148 	.cm_sdma_dynamicdep = 0x4a008a08,
149 	.cm_sdma_sdma_clkctrl = 0x4a008a20,
150 	.cm_memif_clkstctrl = 0x4a008b00,
151 	.cm_memif_dmm_clkctrl = 0x4a008b20,
152 	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
153 	.cm_memif_emif_1_clkctrl = 0x4a008b30,
154 	.cm_memif_emif_2_clkctrl = 0x4a008b38,
155 	.cm_memif_dll_clkctrl = 0x4a008b40,
156 	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
157 	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
158 	.cm_memif_dll_h_clkctrl = 0x4a008b60,
159 	.cm_c2c_clkstctrl = 0x4a008c00,
160 	.cm_c2c_staticdep = 0x4a008c04,
161 	.cm_c2c_dynamicdep = 0x4a008c08,
162 	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
163 	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
164 	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
165 	.cm_l4cfg_clkstctrl = 0x4a008d00,
166 	.cm_l4cfg_dynamicdep = 0x4a008d08,
167 	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
168 	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
169 	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
170 	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
171 	.cm_l3instr_clkstctrl = 0x4a008e00,
172 	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
173 	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
174 	.cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
175 	.cm_ivahd_clkstctrl = 0x4a008f00,
176 
177 	/* cm2.ivahd */
178 	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
179 	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
180 
181 	/* cm2.cam */
182 	.cm_cam_clkstctrl = 0x4a009000,
183 	.cm_cam_iss_clkctrl = 0x4a009020,
184 	.cm_cam_fdif_clkctrl = 0x4a009028,
185 
186 	/* cm2.dss */
187 	.cm_dss_clkstctrl = 0x4a009100,
188 	.cm_dss_dss_clkctrl = 0x4a009120,
189 
190 	/* cm2.sgx */
191 	.cm_sgx_clkstctrl = 0x4a009200,
192 	.cm_sgx_sgx_clkctrl = 0x4a009220,
193 
194 	/* cm2.l3init */
195 	.cm_l3init_clkstctrl = 0x4a009300,
196 	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
197 	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
198 	.cm_l3init_hsi_clkctrl = 0x4a009338,
199 	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
200 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
201 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
202 	.cm_l3init_p1500_clkctrl = 0x4a009378,
203 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
204 	.cm_l3init_usbphy_clkctrl = 0x4a0093e0,
205 
206 	/* cm2.l4per */
207 	.cm_l4per_clkstctrl = 0x4a009400,
208 	.cm_l4per_dynamicdep = 0x4a009408,
209 	.cm_l4per_adc_clkctrl = 0x4a009420,
210 	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
211 	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
212 	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
213 	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
214 	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
215 	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
216 	.cm_l4per_elm_clkctrl = 0x4a009458,
217 	.cm_l4per_gpio2_clkctrl = 0x4a009460,
218 	.cm_l4per_gpio3_clkctrl = 0x4a009468,
219 	.cm_l4per_gpio4_clkctrl = 0x4a009470,
220 	.cm_l4per_gpio5_clkctrl = 0x4a009478,
221 	.cm_l4per_gpio6_clkctrl = 0x4a009480,
222 	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
223 	.cm_l4per_hecc1_clkctrl = 0x4a009490,
224 	.cm_l4per_hecc2_clkctrl = 0x4a009498,
225 	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
226 	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
227 	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
228 	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
229 	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
230 	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
231 	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
232 	.cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
233 	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
234 	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
235 	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
236 	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
237 	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
238 	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
239 	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
240 	.cm_l4per_msprohg_clkctrl = 0x4a009530,
241 	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
242 	.cm_l4per_uart1_clkctrl = 0x4a009540,
243 	.cm_l4per_uart2_clkctrl = 0x4a009548,
244 	.cm_l4per_uart3_clkctrl = 0x4a009550,
245 	.cm_l4per_uart4_clkctrl = 0x4a009558,
246 	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
247 	.cm_l4per_i2c5_clkctrl = 0x4a009568,
248 	.cm_l4sec_clkstctrl = 0x4a009580,
249 	.cm_l4sec_staticdep = 0x4a009584,
250 	.cm_l4sec_dynamicdep = 0x4a009588,
251 	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
252 	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
253 	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
254 	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
255 	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
256 	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
257 	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
258 
259 	/* l4 wkup regs */
260 	.cm_abe_pll_ref_clksel = 0x4a30610c,
261 	.cm_sys_clksel = 0x4a306110,
262 	.cm_wkup_clkstctrl = 0x4a307800,
263 	.cm_wkup_l4wkup_clkctrl = 0x4a307820,
264 	.cm_wkup_wdtimer1_clkctrl = 0x4a307828,
265 	.cm_wkup_wdtimer2_clkctrl = 0x4a307830,
266 	.cm_wkup_gpio1_clkctrl = 0x4a307838,
267 	.cm_wkup_gptimer1_clkctrl = 0x4a307840,
268 	.cm_wkup_gptimer12_clkctrl = 0x4a307848,
269 	.cm_wkup_synctimer_clkctrl = 0x4a307850,
270 	.cm_wkup_usim_clkctrl = 0x4a307858,
271 	.cm_wkup_sarram_clkctrl = 0x4a307860,
272 	.cm_wkup_keyboard_clkctrl = 0x4a307878,
273 	.cm_wkup_rtc_clkctrl = 0x4a307880,
274 	.cm_wkup_bandgap_clkctrl = 0x4a307888,
275 	.prm_vc_val_bypass = 0x4a307ba0,
276 	.prm_vc_cfg_channel = 0x4a307ba4,
277 	.prm_vc_cfg_i2c_mode = 0x4a307ba8,
278 	.prm_vc_cfg_i2c_clk = 0x4a307bac,
279 };
280 
281 struct omap_sys_ctrl_regs const omap4_ctrl = {
282 	.control_status				= 0x4A0022C4,
283 	.control_std_fuse_die_id_0		= 0x4A002200,
284 	.control_std_fuse_die_id_1		= 0x4A002208,
285 	.control_std_fuse_die_id_2		= 0x4A00220C,
286 	.control_std_fuse_die_id_3		= 0x4A002210,
287 	.control_std_fuse_opp_bgap		= 0x4a002260,
288 	.control_status				= 0x4a0022c4,
289 	.control_ldosram_iva_voltage_ctrl	= 0x4A002320,
290 	.control_ldosram_mpu_voltage_ctrl	= 0x4A002324,
291 	.control_ldosram_core_voltage_ctrl	= 0x4A002328,
292 	.control_usbotghs_ctrl			= 0x4A00233C,
293 	.control_padconf_core_base		= 0x4A100000,
294 	.control_pbiaslite			= 0x4A100600,
295 	.control_lpddr2io1_0			= 0x4A100638,
296 	.control_lpddr2io1_1			= 0x4A10063C,
297 	.control_lpddr2io1_2			= 0x4A100640,
298 	.control_lpddr2io1_3			= 0x4A100644,
299 	.control_lpddr2io2_0			= 0x4A100648,
300 	.control_lpddr2io2_1			= 0x4A10064C,
301 	.control_lpddr2io2_2			= 0x4A100650,
302 	.control_lpddr2io2_3			= 0x4A100654,
303 	.control_efuse_1			= 0x4A100700,
304 	.control_efuse_2			= 0x4A100704,
305 	.control_padconf_wkup_base		= 0x4A31E000,
306 };
307