1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Qualcomm APQ8096 sysmap 4 * 5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 6 */ 7 #ifndef _MACH_SYSMAP_APQ8096_H 8 #define _MACH_SYSMAP_APQ8096_H 9 10 #define TLMM_BASE_ADDR (0x1010000) 11 12 /* Strength (sdc1) */ 13 #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) 14 15 /* Clocks: (from CLK_CTL_BASE) */ 16 #define GPLL0_STATUS (0x0000) 17 #define APCS_GPLL_ENA_VOTE (0x52000) 18 19 #define SDCC2_BCR (0x14000) /* block reset */ 20 #define SDCC2_APPS_CBCR (0x14004) /* branch control */ 21 #define SDCC2_AHB_CBCR (0x14008) 22 #define SDCC2_CMD_RCGR (0x14010) 23 #define SDCC2_CFG_RCGR (0x14014) 24 #define SDCC2_M (0x14018) 25 #define SDCC2_N (0x1401C) 26 #define SDCC2_D (0x14020) 27 28 #endif 29