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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4  */
5 
6 #include <common.h>
7 #include <wait_bit.h>
8 #include <asm/io.h>
9 #include <asm/arch/clock_manager.h>
10 
11 DECLARE_GLOBAL_DATA_PTR;
12 
13 static const struct socfpga_clock_manager *clock_manager_base =
14 	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
15 
cm_wait_for_lock(u32 mask)16 void cm_wait_for_lock(u32 mask)
17 {
18 	u32 inter_val;
19 	u32 retry = 0;
20 	do {
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 		inter_val = readl(&clock_manager_base->inter) & mask;
23 #else
24 		inter_val = readl(&clock_manager_base->stat) & mask;
25 #endif
26 		/* Wait for stable lock */
27 		if (inter_val == mask)
28 			retry++;
29 		else
30 			retry = 0;
31 		if (retry >= 10)
32 			break;
33 	} while (1);
34 }
35 
36 /* function to poll in the fsm busy bit */
cm_wait_for_fsm(void)37 int cm_wait_for_fsm(void)
38 {
39 	return wait_for_bit_le32(&clock_manager_base->stat,
40 				 CLKMGR_STAT_BUSY, false, 20000, false);
41 }
42 
set_cpu_clk_info(void)43 int set_cpu_clk_info(void)
44 {
45 	/* Calculate the clock frequencies required for drivers */
46 	cm_get_l4_sp_clk_hz();
47 	cm_get_mmc_controller_clk_hz();
48 
49 	gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
50 	gd->bd->bi_dsp_freq = 0;
51 
52 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
53 	gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
54 #else
55 	gd->bd->bi_ddr_freq = 0;
56 #endif
57 
58 	return 0;
59 }
60 
61 #ifndef CONFIG_SPL_BUILD
do_showclocks(cmd_tbl_t * cmdtp,int flag,int argc,char * const argv[])62 static int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
63 {
64 	cm_print_clock_quick_summary();
65 	return 0;
66 }
67 
68 U_BOOT_CMD(
69 	clocks,	CONFIG_SYS_MAXARGS, 1, do_showclocks,
70 	"display clocks",
71 	""
72 );
73 #endif
74