1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2016-2017 Intel Corporation 4 */ 5 6 #ifndef _RESET_MANAGER_ARRIA10_H_ 7 #define _RESET_MANAGER_ARRIA10_H_ 8 9 #include <dt-bindings/reset/altr,rst-mgr-a10.h> 10 11 void socfpga_watchdog_disable(void); 12 void socfpga_reset_deassert_noc_ddr_scheduler(void); 13 int socfpga_is_wdt_in_reset(void); 14 void socfpga_emac_manage_reset(ulong emacbase, u32 state); 15 int socfpga_reset_deassert_bridges_handoff(void); 16 void socfpga_reset_assert_fpga_connected_peripherals(void); 17 void socfpga_reset_deassert_osc1wd0(void); 18 void socfpga_reset_uart(int assert); 19 int socfpga_bridges_reset(void); 20 21 struct socfpga_reset_manager { 22 u32 stat; 23 u32 ramstat; 24 u32 miscstat; 25 u32 ctrl; 26 u32 hdsken; 27 u32 hdskreq; 28 u32 hdskack; 29 u32 counts; 30 u32 mpumodrst; 31 u32 per0modrst; 32 u32 per1modrst; 33 u32 brgmodrst; 34 u32 sysmodrst; 35 u32 coldmodrst; 36 u32 nrstmodrst; 37 u32 dbgmodrst; 38 u32 mpuwarmmask; 39 u32 per0warmmask; 40 u32 per1warmmask; 41 u32 brgwarmmask; 42 u32 syswarmmask; 43 u32 nrstwarmmask; 44 u32 l3warmmask; 45 u32 tststa; 46 u32 tstscratch; 47 u32 hdsktimeout; 48 u32 hmcintr; 49 u32 hmcintren; 50 u32 hmcintrens; 51 u32 hmcintrenr; 52 u32 hmcgpout; 53 u32 hmcgpin; 54 }; 55 56 /* 57 * SocFPGA Arria10 reset IDs, bank mapping is as follows: 58 * 0 ... mpumodrst 59 * 1 ... per0modrst 60 * 2 ... per1modrst 61 * 3 ... brgmodrst 62 * 4 ... sysmodrst 63 */ 64 #define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) 65 #define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) 66 #define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) 67 #define RSTMGR_NAND RSTMGR_DEFINE(1, 5) 68 #define RSTMGR_QSPI RSTMGR_DEFINE(1, 6) 69 #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) 70 #define RSTMGR_DMA RSTMGR_DEFINE(1, 16) 71 #define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) 72 #define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) 73 #define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) 74 #define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) 75 #define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) 76 #define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) 77 #define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4) 78 #define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5) 79 #define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) 80 #define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) 81 #define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) 82 83 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1) 84 #define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0) 85 #define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1) 86 #define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2) 87 #define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3) 88 #define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4) 89 #define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5) 90 #define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6) 91 #define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7) 92 #define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8) 93 #define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9) 94 #define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10) 95 #define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11) 96 #define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12) 97 #define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13) 98 #define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14) 99 #define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15) 100 #define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16) 101 #define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17) 102 #define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18) 103 #define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19) 104 #define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20) 105 #define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21) 106 #define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22) 107 #define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24) 108 #define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25) 109 #define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26) 110 #define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27) 111 #define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28) 112 #define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29) 113 #define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30) 114 #define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31) 115 116 #define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0) 117 #define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1) 118 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2) 119 #define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3) 120 #define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4) 121 #define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5) 122 #define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8) 123 #define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9) 124 #define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10) 125 #define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11) 126 #define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12) 127 #define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16) 128 #define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17) 129 #define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24) 130 #define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25) 131 #define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26) 132 133 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0) 134 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1) 135 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2) 136 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3) 137 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4) 138 #define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5) 139 #define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6) 140 141 #define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0) 142 #define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1) 143 #define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2) 144 #define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3) 145 146 #endif /* _RESET_MANAGER_ARRIA10_H_ */ 147